Patents by Inventor Ki Jik Lee
Ki Jik Lee has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7525847Abstract: A semiconductor device includes at least two transistors and a charge-trapping structure. The charge-trapping structure traps charges, which are moved from a selected transistor toward a non-selected transistor, adjacent to the selected transistor among the transistors, thereby preventing a threshold voltage of the non-selected transistor from being increased. Thus, the charge-trapping structure traps the charges so that an increase of the threshold voltage of the non-selected voltage is suppressed.Type: GrantFiled: November 18, 2005Date of Patent: April 28, 2009Assignee: Samsung Electronics Co., Ltd.Inventors: Soo-Cheol Lee, Ki-Jik Lee
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Publication number: 20060109709Abstract: A semiconductor device includes at least two transistors and a charge-trapping structure. The charge-trapping structure traps charges, which are moved from a selected transistor toward a non-selected transistor, adjacent to the selected transistor among the transistors, thereby preventing a threshold voltage of the non-selected transistor from being increased. Thus, the charge-trapping structure traps the charges so that an increase of the threshold voltage of the non-selected voltage is suppressed.Type: ApplicationFiled: November 18, 2005Publication date: May 25, 2006Inventors: Soo-Cheol Lee, Ki-Jik Lee
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Patent number: 6573573Abstract: Mask ROM and method for fabricating the same, are disclosed, which is operative at a fast speed and a low voltage, including a semiconductor substrate, a first insulating film formed on the semiconductor substrate, conductive layer patterns formed on the first insulating film, a first, and a second impurity regions formed in the semiconductor substrate on both sides of the conductive layer patterns, a second insulating film formed on the first insulating film inclusive of the conductive layer patterns, a contact hole formed in the second insulating film on the conductive layer patterns, a plug formed in each of the contact holes, and wordlines formed the second insulating film inclusive of the plugs.Type: GrantFiled: August 15, 2001Date of Patent: June 3, 2003Assignee: Hyundai Electronics Industries Co., Ltd.Inventor: Ki Jik Lee
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Patent number: 6531353Abstract: A method for fabricating a semiconductor device is disclosed, which reduces defects of a device by improving the process to improve the production yield.Type: GrantFiled: July 17, 2001Date of Patent: March 11, 2003Assignee: Hynix Semiconductor, Inc.Inventor: Ki Jik Lee
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Patent number: 6384449Abstract: Nonvolatile memory and method for fabricating the same, which can prevent damages to a diffusion region between a selection transistor and a memory cell transistor and reduce a cell size, the nonvolatile memory including a semiconductor substrate having a selection transistor and a cell transistor defined thereon, a line form of a first selection gate line formed on the selection transistor region in one direction and a floating gate formed on the cell transistor region in a fixed pattern, an insulating film and a second gate line formed on the first selection gate line at fixed intervals, and an insulating film and a control gate line over the insulating film including the floating gate in a direction the same with the first gate line, impurity regions formed in one region in the semiconductor substrate on both sides of the control gate line and the first selection gate line, a first planar protection film having first contact holes one each to the first selection gate line and to the impurity region, a contType: GrantFiled: April 27, 2001Date of Patent: May 7, 2002Assignee: Hyundai Electronics Industries Co., LTDInventors: Ki Jik Lee, Jae Min Yu
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Publication number: 20020045305Abstract: A method for fabricating a semiconductor device is disclosed, which reduces defects of a device by improving the process to improve the production yield.Type: ApplicationFiled: July 17, 2001Publication date: April 18, 2002Inventor: Ki Jik Lee
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Publication number: 20020025611Abstract: Mask ROM and method for fabricating the same, are disclosed, which is operative at a fast speed and a low voltage, including a semiconductor substrate, a first insulating film formed on the semiconductor substrate, conductive layer patterns formed on the first insulating film, a first, and a second impurity regions formed in the semiconductor substrate on both sides of the conductive layer patterns, a second insulating film formed on the first insulating film inclusive of the conductive layer patterns, a contact hole formed in the second insulating film on the conductive layer patterns, a plug formed in each of the contact holes, and wordlines formed the second insulating film inclusive of the plugs.Type: ApplicationFiled: August 15, 2001Publication date: February 28, 2002Applicant: Hyundai Electronics Industries Co., Ltd.Inventor: Ki Jik Lee
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Patent number: 6303442Abstract: Mask ROM and method for fabricating the same, are disclosed, which is operative at a fast speed and a low voltage, including a semiconductor substrate, a first insulating film formed on the semiconductor substrate, conductive layer patterns formed on the first insulating film, a first, and a second impurity regions formed in the semiconductor substrate on both sides of the conductive layer patterns, a second insulating film formed on the first insulating film inclusive of the conductive layer patterns, a contact hole formed in the second insulating film on the conductive layer patterns, a plug formed in each of the contact holes, and wordlines formed the second insulating film inclusive of the plugs.Type: GrantFiled: April 27, 1999Date of Patent: October 16, 2001Assignee: Hyundai Electronics Industries Co., Ltd.Inventor: Ki Jik Lee
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Publication number: 20010023954Abstract: Nonvolatile memory and method for fabricating the same, which can prevent damages to a diffusion region between a selection transistor and a memory cell transistor and reduce a cell size, the nonvolatile memory including a semiconductor substrate having a selection transistor and a cell transistor defined thereon, a line form of a first selection gate line formed on the selection transistor region in one direction and a floating gate formed on the cell transistor region in a fixed pattern, an insulating film and a second gate line formed on the first selection gate line at fixed intervals, and an insulating film and a control gate line over the insulating film including the floating gate in a direction the same with the first gate line, impurity regions formed in one region in the semiconductor substrate on both sides of the control gate line and the first selection gate line, a first planar protection film having first contact holes one each to the first selection gate line and to the impurity region, a contType: ApplicationFiled: April 27, 2001Publication date: September 27, 2001Applicant: Hyundai Electronics Industries Co., Ltd.Inventors: Ki Jik Lee, Jae Min Yu
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Patent number: 6255155Abstract: Nonvolatile memory and method for fabricating the same, which can prevent damages to a diffusion region between a selection transistor and a memory cell transistor and reduce a cell size, the nonvolatile memory including a semiconductor substrate having a selection transistor and a cell transistor defined thereon, a line form of a first selection gate line formed on the selection transistor region in one direction and a floating gate formed on the cell transistor region in a fixed pattern, an insulating film and a second gate line formed on the first selection gate line at fixed intervals, and an insulating film and a control gate line over the insulating film including the floating gate in a direction the same with the first gate line, impurity regions formed in one region in the semiconductor substrate on both sides of the control gate line and the first selection gate line, a first planar protection film having first contact holes one each to the first selection gate line and to the impurity region, a contType: GrantFiled: April 21, 1999Date of Patent: July 3, 2001Assignee: Hyundai Electronics Industries Co., Ltd.Inventors: Ki Jik Lee, Jae Min Yu
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Patent number: 6221722Abstract: A method of fabricating a mask ROM that includes forming a plurality of buried bitlines in an upper surface of a semiconductor substrate at fixed intervals and a plurality of wordlines on the semiconductor substrate perpendicular to the buried bitlines; forming an interlayer insulating film having a bitline contact hole on an entire first surface of the semiconductor substrate inclusive of the wordlines; forming a metal pattern in contact with the buried bitlines through the contact hole; forming a ROM code mask on the metal pattern; forming a plurality of ROM code ion implantation regions by selectively etching the interlayer insulating film with the ROM code mask; and forming a protection film on an entire second surface of the semiconductor substrate by implanting ROM code ions in the ROM code ion implantation regions.Type: GrantFiled: August 21, 2000Date of Patent: April 24, 2001Assignee: Hyundai Electronics Industries Co., Ltd.Inventor: Ki Jik Lee
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Patent number: 6157069Abstract: A method of fabricating a mask ROM includes forming a trench on a first conductivity type semiconductor substrate, implanting a second conductivity type impurity ion in at least a surface portion of the semiconductor substrate where the trench is formed, forming an insulating oxide layer on a surface of the semiconductor substrate, including a surface of the trench, forming gate oxide layers of both sides of the trench, forming first and second gates on the gate, oxide layers and forming a first conductivity type channel by implanting a first conductivity type impurity ion in one side of the trench. As such, the resulting mask ROM includes two transistors on either side of a trench having channels along the side walls of the trench. The resulting mask ROM has a reduced surface width, enhancing integration.Type: GrantFiled: November 30, 1999Date of Patent: December 5, 2000Assignee: Hyundai Electronics Industries Co., Ltd.Inventors: Bong-Jo Shin, Ki-Jik Lee
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Patent number: 6022779Abstract: A method of fabricating a mask ROM includes forming a trench on a first conductivity type semiconductor substrate, implanting a second conductivity type impurity ion in at least a surface portion of the semiconductor substrate where the trench is formed, forming an insulating oxide layer on a surface of the semiconductor substrate, including a surface of the trench, forming gate oxide layers of both sides of the trench, forming first and second gates on the gate oxide layers and forming a first conductivity type channel by implanting a first conductivity type impurity ion in one side of the trench. As such, the resulting mask ROM includes two transistors on either side of a trench having channels along the side walls of the trench. The resulting mask ROM has a reduced surface width, enhancing integration.Type: GrantFiled: May 22, 1998Date of Patent: February 8, 2000Assignee: LG Semicon Co., Ltd.Inventors: Bong-Jo Shin, Ki-Jik Lee