Abstract: A storage node may include a bottom electrode contact layer, a phase change layer connected to the bottom electrode contact layer, and a top electrode layer connected to the phase change layer. The bottom electrode contact layer may protrude toward the phase change layer. A phase change memory device may include a switching device and the storage node. The switching device may be connected to the bottom electrode contact layer. A method of manufacturing the storage node may include forming a via hole in an insulating interlayer, at least partially filling the via hole to form a bottom electrode contact layer, protruding the bottom electrode contact layer from the via hole, and forming a phase change layer that covers the bottom electrode contact layer. A method of manufacturing a phase change memory device may include forming the switching device on a substrate and manufacturing the storage node.

Abstract: A storage node, a phase change random access memory having an improved structure to improve adhesion of a phase change material layer and methods of fabricating the same are provided. The storage node may include a bottom electrode, a top electrode, a phase change material layer inserted between the bottom electrode and the top electrode, and an adhesion interfacial layer inserted between the bottom electrode and the phase change material layer. The phase change random access memory may include a switching device and the storage node connected to the switching device.

Abstract: A phase change RAM (PRAM) including a resistance element having a diode function, and methods of fabricating and operating the same are provided. The PRAM may include a substrate, a phase change diode layer formed on the substrate and an upper electrode formed on the phase change diode layer. The phase change diode layer may include a material layer doped with first impurities, and a phase change layer which is stacked on the doped layer. The phase change layer may show characteristics of a semiconductor material doped with impurities having an opposite conductive type to that of the first impurities.

Abstract: A phase change memory device includes a switch and a storage node connected to the switch. The storage node includes a first electrode, a phase change layer and a second electrode. The phase change layer is formed of an InSbTe compound doped with Ge. In a method of operating a phase change memory including a switch and a storage node, the switch is maintained in an on state, and a first current is applied to the storage node.

Abstract: There is provided a source driver capable of controlling the timing of source line driving signals in a liquid crystal display device. The source driver includes a plurality of output circuits, each output circuit including an output buffer and a switch. The output buffer amplifies an analog image signal, and the switch outputs the amplified analog image signal as a source line driving signal in response to a control signal. The source driver further comprises a control circuit for generating the control signal, the control circuit comprising: a delay circuit delaying a switch signal and generating a delayed switch signal; and a multiplexer selecting one of the switch signal and the delayed switch signal in response to a selection signal and outputting the selected signal as the control signal.

Abstract: A source driver output circuit of a thin film transistor (TFT) liquid crystal display (LCD) includes first through n-th voltage generators, first through n-th switching portions, first through n-th sub switching portions, and a switching circuit. The voltage generators receive first through n-th corresponding input voltages and generate first through n-th sub input voltages. The switching portions generate the sub input voltages as first through n-th corresponding output voltages when activated, or cut off the sub input voltages when deactivated. The sub switching portions connect predetermined share lines to the output voltages when activated, or cut off the predetermined share lines when deactivated. The switching circuit maintains each of the share line voltages equally at an intermediate voltage level that is between the share line voltages. Therefore, the slew rate of a signal input to the panel from the source driver can be improved, and current consumption in the source driver can be reduced.

Abstract: A source driver output circuit of a thin film transistor (TFT) liquid crystal display (LCD) includes first through n-th voltage generators, first through n-th switching portions, first through n-th sub switching portions, and a voltage-generating portion. The voltage generators receive first through n-th corresponding input voltages and generate first through n-th sub input voltages. The switching portions generate the sub input voltages as first through n-th corresponding output voltages when activated, or cut off the sub input voltages when deactivated. The sub switching portions connect predetermined share lines to the output voltages when activated, or cut off the predetermined share lines when deactivated. The voltage-generating portion receives predetermined first and second voltages and applies predetermined precharge voltages to the share lines. Therefore, the slew rate of a signal input to the panel from the source driver can be improved, and current consumption in the source driver can be reduced.

Abstract: A cleaning method of an apparatus for manufacturing a semiconductor device includes providing a first cleaning gas and a second cleaning gas into a chamber, and forming a mixture of the first cleaning gas and the second cleaning gas, wherein the first cleaning gas includes a fluorocarbon gas and an oxygen gas and the second cleaning gas includes nitrogen, activating the mixture of the first cleaning gas and the second cleaning gas by a high frequency power, and exhausting residues cleaned by the activated mixture and remaining gases.

Abstract: A source driver output circuit of a thin film transistor (TFT) liquid crystal display (LCD) includes first through n-th voltage generators, first through n-th switching portions, first through n-th sub switching portion, and a voltage-generating portion. The first through n-th (where n is even integer) voltage generators receive first through n-th corresponding input voltages and generate first through n-th sub input voltages. The first through n-th switching portions generate the first through n-th sub input voltages as first through n-th corresponding output voltages when activated or cut off the first through n-th sub input voltages when deactivated. The first through n-th sub switching portions connect predetermined share lines to the first through n-th output voltages when activated or cut off the predetermined share lines when deactivated. The voltage-generating portion receives predetermined first and second voltages and applies predetermined precharge voltages to the share lines.

Abstract: A semiconductor device manufacturing method is provided. In this method for interconnecting conductive layers, an insulating layer is formed over the surface of a semiconductor substrate having conductive layers formed thereon. The insulating layer is removed from over the conductive layers and a silicon layer is coated on the overall surface of the resultant structure. The insulating layer and some silicon are then removed from an area except for the area from a first conductive layer through a second conductive layer, and a refractory metal layer is formed on the overall surface of the resultant structure. This refractory metal is used for silicidation. A metal silicide layer is then formed from the first conductive layer through the second conductive layer by thermally treating the refractory metal layer.

Abstract: A full CMOS SRAM cell having the capability of having a reduced aspect ratio is described. The SRAM cell includes first and second transfer transistors of n-channel types, first and second driving transistors of the n-channel types and first and second load transistors of p-channel types. Each of the transistors has source and drain regions on opposite sides of a channel region formed in a semiconductor substrate and a gate over the channel region. The cell includes a first common region defined by the drain regions of the first transfer transistor and the first driving transistor connected in series therethrough. A second common region is defined by the drain regions of the second transfer transistor and the second driving transistor connected in series therethrough. The drain region of the first load transistor is disposed adjacent to the first common region between the first and second common regions.

Abstract: There is disclosed a method for making array capable of realizing large output and large-scale integration by using a heterogenous film which can electrically insulate between LEDs, (LEDs) by the diffusion of an impurity into a substrate. The improved LED array manufacturing method includes the steps of: forming a luminescent layer, of a first conductivity type, a transparent layer and a cap-layer over the semiconductor substrate, forming of a cap layer made into a given pattern by etching a given portion of said cap layer; forming of a diffusion region converted into the first conductivity type by the injection of an impurity into a given portion of the transparent layer; forming an oxide film on the entire surface except the area where the cap layer is covering the transparent layer 13; and forming an electrode over the cap layer and a common electrode under the semiconductor substrate.

Abstract: There is disclosed a method for making a light-emitting diode array capable of realizing large output and large-scale integration by using a heterogenous film which can electrically insulate between LEDs, (LEDs) by the diffusion of an impurity into a substrate. The improved LED array manufacturing method includes the steps of: forming a luminescent layer, of a first conductivity type, a transparent layer and a cap-layer over the semiconductor substrate; forming of a cap layer made into a given pattern by etching a given portion of said cap layer; forming of a diffusion region converted into the first conductivity type by the injection of an impurity into a given portion of the transparent layer; forming an oxide film on the entire surface except the area where the cap layer is covering the transparent layer; and forming an electrode over the cap layer and a common electrode under the semiconductor substrate.

Abstract: A method of making an LED array capable of enhancing an internally generated light density with heterojunction by supporting the LED array with a current injection region by growing heterogeneous film and diffusing a zinc impurity. The improved LED array is capable of producing a high optical power by radiating efficiently a generated light beam without disturbance.

Abstract: A device and method for liquid-phase thin film epitaxial growth are disclosed wherein yield and quality of semiconductors in the fabrication sequences are improved. The device comprises an electric furnace which is disposed outside a quartz tube, a plurality of boats which are disposed within the quartz tube in accordance with a sort of melting liquids and a plurality of auxiliary heating devices are disposed around the boats with a power source independent from the electric furnace.