Abstract: A method for manufacturing a semiconductor device includes forming features of a first mold pattern on a substrate including a first region and a second region, and forming a first insulation layer covering the first mold pattern from the first region to the second region. The method further includes forming a photoresist pattern on the first insulation layer in the second region, forming a second insulation layer covering the first insulation layer in the first region and the photoresist pattern in the second region from the first region to the second region, etching the second insulation layer, removing the photoresist pattern, and forming a first double patterning technology pattern having a first width in the first region and a second DPT pattern having a second width in the second region, wherein the second width is different from the first width.

Abstract: A semiconductor device including a substrate with a first trench, a first insulation liner on inner flanks of the first trench, and a second insulation liner on inner flanks of a first sub trench, the first insulation trench defined by the first insulation liner in the first trench, a top level of the second insulation liner that adjoins the inner flanks of the first sub trench in a direction perpendicular to a top surface of the substrate being different from the top surface of the substrate outside the first trench, may be provided.

Abstract: A method for fabricating a semiconductor device includes forming a device isolation film on a substrate between first and second regions, forming first and second sealing films, such that an etch selectivity of the second sealing film is smaller than that of the first sealing film, patterning the first and second sealing films to expose the second region and a portion of the device isolation film, such that an undercut is defined under a lower surface of the second sealing film, forming a filling film filling the undercut, a thickness of the filling film being thicker on a side surface of the second sealing film than on an upper surface thereof, removing a portion of the filling film to form a filling spacer in the undercut, forming a high-k dielectric film and a metal film on the filling spacer, and patterning the high-k dielectric film and the metal film.

Abstract: A semiconductor device includes a substrate including a cell active region and a peripheral active region, a direct contact arranged on a cell insulating pattern formed on the substrate and connected to the cell active region, a bit line structure including a thin conductive pattern, contacting a top surface of the direct contact and extending in one direction, and a peripheral gate structure in the peripheral active region. The peripheral gate structure include a stacked structure of a peripheral gate insulating pattern and a peripheral gate conductive pattern, the thin conductive pattern includes a first material and the peripheral gate conductive pattern include the first material, and a level of an upper surface of the thin conductive pattern is lower than a level of an upper surface of the peripheral gate conductive pattern.

Abstract: Methods for manufacturing a semiconductor device include forming a gate line extending in a first direction in a substrate, and an impurity region on a side surface of the gate line, forming an insulating film pattern on the substrate, the insulating film pattern extending in the first direction and comprising a first through-hole that is configured to expose the impurity region, forming a barrier metal layer on the first through-hole, forming a conductive line contact that fills the first through-hole and that is electrically connected to the impurity region, fowling a first mask pattern on the conductive line contact and the insulating film pattern, the first mask pattern extending in a second direction that is different from the first direction and the first mask pattern comprising a first opening, and removing corners of the barrier metal layer by partially etching the barrier metal layer.

Abstract: A semiconductor device includes a substrate having an active region defined by a device isolation layer and at least a gate trench linearly extending in a first direction to cross the active region, the active region having a gate area at a bottom of the gate trench and a junction area at a surface of the substrate. The device further may include a first conductive line filling the gate trench and extending in the first direction, the first conductive line having a buried gate structure on the gate area of the active region. The device also may include a junction including implanted dopants at the junction area of the active region, and a junction separator on the device isolation layer and defining the junction. The junction separator may be formed of an insulative material and have an etch resistance greater than that of the device isolation layer.

Abstract: The present disclosure relates to a sensor network, machine type communication (MTC), machine-to-machine (M2M) communication, and technology for internet of things (IoT). The present disclosure may be applied to intelligent services based on the above technologies, such as smart home, smart building, smart city, smart car, connected car, health care, digital education, smart retail, security and safety services. A method for transmitting a beacon frame signal by a transmitting node in a wireless communication network is provided.

Abstract: The present disclosure relates to a sensor network, machine type communication (MTC), machine-to-machine (M2M) communication, and technology for internet of things (IoT). The present disclosure may be applied to intelligent services based on the above technologies, such as smart home, smart building, smart city, smart car, connected car, health care, digital education, smart retail, security and safety services. A method for detecting a counterfeit advertiser by a server includes detecting a random delay time or a cumulative interval for a reference device based on a time stamp for an advertisement packet received from the reference device, and detecting a random delay time or a cumulative interval for a receiving device other than the reference device based on a time stamp for an advertisement packet received from the receiving device.

Abstract: Methods for manufacturing a semiconductor device include forming a gate line extending in a first direction in a substrate, and an impurity region on a side surface of the gate line, forming an insulating film pattern on the substrate, the insulating film pattern extending in the first direction and comprising a first through-hole that is configured to expose the impurity region, forming a barrier metal layer on the first through-hole, forming a conductive line contact that fills the first through-hole and that is electrically connected to the impurity region, forming a first mask pattern on the conductive line contact and the insulating film pattern, the first mask pattern extending in a second direction that is different from the first direction and the first mask pattern comprising a first opening, and removing corners of the barrier metal layer by partially etching the barrier metal layer.

Abstract: Methods for manufacturing a semiconductor device include forming a gate line extending in a first direction in a substrate, and an impurity region on a side surface of the gate line, forming an insulating film pattern on the substrate, the insulating film pattern extending in the first direction and comprising a first through-hole that is configured to expose the impurity region, forming a barrier metal layer on the first through-hole, forming a conductive line contact that fills the first through-hole and that is electrically connected to the impurity region, forming a first mask pattern on the conductive line contact and the insulating film pattern, the first mask pattern extending in a second direction that is different from the first direction and the first mask pattern comprising a first opening, and removing corners of the barrier metal layer by partially etching the barrier metal layer.

Abstract: A semiconductor device includes a substrate including a cell area and a background area, the background area surrounding the cell area, a plurality of active patterns in the cell area along a first direction, the active patterns being defined by a device isolation layer, and a background pattern filling the background area to surround the cell area, wherein the active patterns include a first active pattern most adjacent to an edge of the cell area, and a second active pattern separated from the first active pattern in a second direction intersecting the first direction, the second active pattern being separated from the background area.

Abstract: A method for manufacturing a semiconductor device includes forming features of a first mold pattern on a substrate including a first region and a second region, and forming a first insulation layer covering the first mold pattern from the first region to the second region. The method further includes forming a photoresist pattern on the first insulation layer in the second region, forming a second insulation layer covering the first insulation layer in the first region and the photoresist pattern in the second region from the first region to the second region, etching the second insulation layer, removing the photoresist pattern, and forming a first double patterning technology pattern having a first width in the first region and a second DPT pattern having a second width in the second region, wherein the second width is different from the first width.

Abstract: A semiconductor device includes an active pattern. A first source or drain region and a second source or drain region are formed at upper portions of the active pattern. The first source or drain region and the second source or drain region are each disposed adjacent to the gate structure. The gate structure is disposed between the first source or drain region and the second source or drain region. A conductive line is electrically connected to the first source or drain region, the conductive line including a first portion and a second portion. A width of the first portion is greater than a width of the second portion. The width of the first and second portions of the conductive line is measured along a first direction in plan view. A conductive contact is electrically connected to the second source or drain region.

Abstract: The present disclosure relates to a sensor network, machine type communication (MTC), machine-to-machine (M2M) communication, and technology for internet of things (IoT). The present disclosure may be applied to intelligent services based on the above technologies, such as smart home, smart building, smart city, smart car, connected car, health care, digital education, smart retail, security and safety services. A method for detecting a counterfeit advertiser by a server includes detecting a random delay time or a cumulative interval for a reference device based on a time stamp for an advertisement packet received from the reference device, and detecting a random delay time or a cumulative interval for a receiving device other than the reference device based on a time stamp for an advertisement packet received from the receiving device.

Abstract: A semiconductor device includes a substrate including spaced-apart active regions, and device isolating regions isolating the active regions from each other, and a pillar array pattern including a plurality of pillar patterns overlapping the active regions, the plurality of pillar patterns being spaced apart from each other at an equal distance in a first direction and in a second direction intersecting the first direction, wherein the plurality of pillar patterns include first pillar patterns and second pillar patterns disposed alternatingly in the first direction and in the second direction, a shape of a horizontal cross section of the first pillar patterns being different from a shape of a horizontal cross section of the second pillar patterns.

Abstract: A semiconductor device includes a first contact plug on a substrate, a first lower electrode disposed on the first contact plug and extended in a thickness direction of the substrate, a first supporter pattern on the first lower electrode and including an upper surface and a lower surface, the upper surface of the first supporter pattern being higher than a top surface of the first lower electrode, a dielectric film on the first lower electrode, the upper surface of the first supporter pattern and the lower surface of the first supporter pattern and an upper electrode disposed on the dielectric film.

Abstract: In a method of forming active patterns, first patterns are formed in a first direction on a cell region of a substrate, and a second pattern is formed on a peripheral circuit region of the substrate. The first pattern extends in a third direction crossing the first direction. First masks are formed in the first direction on the first patterns, and a second mask is formed on the second pattern. The first mask extends in a fourth direction crossing the third direction. Third masks are formed between the first masks extending in the fourth direction. The first and second patterns are etched using the first to third masks to form third and fourth patterns. Upper portions of the substrate are etched using the third and fourth patterns to form first and second active patterns in the cell and peripheral circuit regions.

Abstract: In a method of forming active patterns, first patterns are formed in a first direction on a cell region of a substrate, and a second pattern is formed on a peripheral circuit region of the substrate. The first pattern extends in a third direction crossing the first direction. First masks are formed in the first direction on the first patterns, and a second mask is formed on the second pattern. The first mask extends in a fourth direction crossing the third direction. Third masks are formed between the first masks extending in the fourth direction. The first and second patterns are etched using the first to third masks to form third and fourth patterns. Upper portions of the substrate are etched using the third and fourth patterns to form first and second active patterns in the cell and peripheral circuit regions.

Abstract: A method of manufacturing a semiconductor device includes forming an isolation pattern on a substrate to define active patterns each having a first contact region at a center portion thereof and second and third contact regions at edge portions thereof. The method further includes forming a buried gate structure at upper portions of the isolation pattern and the active patterns, forming a first insulation layer on the isolation pattern and the active patterns, and etching a portion of the first insulation layer and an upper portion of the first contact region to form a preliminary opening exposing the first contact region. The method still further includes etching the isolation pattern to form an opening, forming an insulation pattern on a sidewall of the opening, and forming a wiring structure contacting the first contact region in the opening.

Abstract: A semiconductor memory device and a manufacturing method of the semiconductor memory device are provided. The semiconductor memory device can include a substrate in which a cell area and a peripheral area are defined, a first gate insulating layer on the peripheral area, and a poly gate layer on the first gate insulating layer to form a combined stack, wherein the combined stack of the first gate insulating layer and the first poly gate layer is absent from the cell area.