Abstract: A frequency detector includes an error measurement unit measuring a time interval between zero-crossing points of an input signal that is modulated. An error conversion unit quantizes the measured time interval using one of modulation time intervals. An error calculation unit calculates a frequency error based upon a difference between the measured time interval and the quantized time interval. An error generation control unit controls whether to output the frequency error based upon the quantized time interval, the calculated frequency error, and a predetermined critical value.

Abstract: A frequency detector includes an error measurement unit measuring a time interval between zero-crossing points of an input signal that is modulated. An error conversion unit quantizes the measured time interval using one of modulation time intervals. An error calculation unit calculates a frequency error based upon a difference between the measured time interval and the quantized time interval. An error generation control unit controls whether to output the frequency error based upon the quantized time interval, the calculated frequency error, and a predetermined critical value.

Abstract: A semiconductor memory device comprises a plurality of memory cell arrays, a plurality of sense amplifiers, a connection unit, a driver and an over-driver. The plurality of memory cell arrays comprise a plurality of memory cells. The plurality of sense amplifiers sense and amplify data stored in the plurality of memory cells. The connection unit selectively connects the plurality of sense amplifiers to the plurality of memory cell arrays. The driver drives the sense amplifier to a predetermined voltage. The over-driver applies an overdrive voltage to the driver for a predetermined time after the sense amplifier is temporarily separated from the selected memory cell array. In the semiconductor device since data in a bitline can be rapidly amplified, the restoration time of data stored in a memory cell is reduced, and the parameter tRCD. Accordingly, the operation speed of the semiconductor memory device can be improved.

Abstract: A register controlled delay locked loop (DLL) usable in a semiconductor device is provided. The register controlled delay locked loop includes an internal clock generating unit generating a delayed clock signal and a reference clock signal, a first delay unit compensating for an amount of delay caused by a signal transmission path of the delayed clock signal, a phase comparator detecting a difference between the reference clock signal and the delayed clock signal and thereby generating a detection signal, a controller having a plurality of second delay units for controlling an amount of delay of the delayed clock signal in response to the detection signal, a driver driving a DLL clock signal, and an enable signal generator enabling the driver in response to an activation or non-activation signal of the semiconductor device.

Abstract: The present invention provides a semiconductor memory device for reducing operation noise, as a sense amplifier in accordance with the present invention senses and amplifies a supplied data signal of a bit line pair on high speed. For this object, the semiconductor memory device includes a first cell array including a plurality of unit cells to be selected by an address signal; a sense amplifying unit for sensing and amplifying voltage level of a bit line connected to the plurality of the unit cells; a switching unit for connecting or disconnecting the sense amplifying unit to the bit line; and a sense amplifying connection unit for controlling the switching unit for connecting or disconnecting the sense amplifying unit to the first cell array by increasing or decreasing an amount of current throughout the switching unit in response to the address signal.

Abstract: A register controlled delay locked loop (DLL) usable in a semiconductor device is provided. The register controlled delay locked loop includes an internal clock generating unit generating a delayed clock signal and a reference clock signal, a first delay unit compensating for an amount of delay caused by a signal transmission path of the delayed clock signal, a phase comparator detecting a difference between the reference clock signal and the delayed clock signal and thereby generating a detection signal, a controller having a plurality of second delay units for controlling an amount of delay of the delayed clock signal in response to the detection signal, a driver driving a DLL clock signal, and an enable signal generator enabling the driver in response to an activation or non-activation signal of the semiconductor device.

Abstract: A semiconductor memory device comprises a plurality of memory cell arrays, a plurality of sense amplifiers, a connection means, a driver and an over-driver. The plurality of memory cell arrays comprise a plurality of memory cells. The plurality of sense amplifiers sense and amplify data stored in the plurality of memory cells. The connection means selectively connects the plurality of sense amplifiers to the plurality of memory cell arrays. The driver drives the sense amplifier to a predetermined voltage. The over-driver applies an overdrive voltage to the driver for a predetermined time after the sense amplifier is temporarily separated from the selected memory cell array. In the semiconductor device since data in a bitline can be rapidly amplified, the restoration time of data stored in a memory cell is reduced, and the parameter tRCD. Accordingly, the operation speed of the semiconductor memory device can be improved.

Abstract: A resister controlled delay locked loop (DLL) is provided which is capable of reducing current consumption by operating the DLL loop when the semiconductor device is only at an operation mode. A semiconductor device having the register controlled DLL and an internal circuit synchronized with a DLL clock signal output from the register controlled DLL, includes an enable signal generator generating an enable signal for the register controlled DLL to control a generation of the DLL clock signal in response to an activation or non-activation signal of the semiconductor device.

Abstract: The present invention provides a semiconductor memory device for reducing operation noise, as a sense amplifier in accordance with the present invention senses and amplifies a supplied data signal of a bit line pair on high speed. For this object, the semiconductor memory device includes a first cell array including a plurality of unit cells to be selected by an address signal; a sense amplifying unit for sensing and amplifying voltage level of a bit line connected to the plurality of the unit cells; a switching unit for connecting or disconnecting the sense amplifying unit to the bit line; and a sense amplifying connection unit for controlling the switching unit for connecting or disconnecting the sense amplifying unit to the first cell array by increasing or decreasing an amount of current throughout the switching unit in response to the address signal.

Abstract: A resister controlled delay locked loop (DLL) is provided which is capable of reducing current consumption by operating the DLL loop when the semiconductor device is only at an operation mode. A semiconductor device having the register controlled DLL and an internal circuit synchronized with a DLL clock signal output from the register controlled DLL, includes an enable signal generator generating an enable signal for the register controlled DLL to control a generation of the DLL clock signal in response to an activation or non-activation signal of the semiconductor device.