Patents by Inventor Ki Sik Im

Ki Sik Im has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11994277
    Abstract: Proposed is a detachable lighting device including lighting units. The positions of the lighting units are changeable along a mounting rail within an interior space. The number of the lighting units and the mounting positions of the lighting units are adjustable. Accordingly, occupants within the interior space adjust light distribution as desired by each occupant.
    Type: Grant
    Filed: November 11, 2022
    Date of Patent: May 28, 2024
    Assignees: HYUNDAI MOTOR COMPANY, KIA CORPORATION, LS Automotive Technologies Co., Ltd.
    Inventors: Sung Ho Park, Ki Bong Lee, Su Gyeong Im, Hee Youl An, Kyeong Sik Kim
  • Publication number: 20240085007
    Abstract: Proposed is a detachable lighting device including lighting units. The positions of the lighting units are changeable along a mounting rail within an interior space. The number of the lighting units and the mounting positions of the lighting units are adjustable. Accordingly, occupants within the interior space adjust light distribution as desired by each occupant.
    Type: Application
    Filed: November 11, 2022
    Publication date: March 14, 2024
    Applicants: HYUNDAI MOTOR COMPANY, KIA CORPORATION, LS Automotive Technologies Co., Ltd.
    Inventors: Sung Ho Park, Ki Bong Lee, Su Gyeong Im, Hee Youl An, Kyeong Sik Kim
  • Patent number: 9299800
    Abstract: The methods may include forming a first material layer on a substrate, increasing electric resistance of the first material layer, and forming a source pattern and a drain pattern, which are spaced apart from each other, on the first material layer, a band gap of the source and drain patterns greater than a band gap of a first material layer.
    Type: Grant
    Filed: April 15, 2015
    Date of Patent: March 29, 2016
    Assignees: Samsun Electronics Co., Ltd., Kyungpook National University Industry-Academic Cooperation
    Inventors: Hyuk-soon Choi, Jung-hee Lee, Jai-kwang Shin, Jae-joon Oh, Jong-bong Ha, Jong-seob Kim, In-jun Hwang, Ki-ha Hong, Ki-sik Im, Ki-won Kim, Dong-seok Kim
  • Publication number: 20150221746
    Abstract: The methods may include forming a first material layer on a substrate, increasing electric resistance of the first material layer, and forming a source pattern and a drain pattern, which are spaced apart from each other, on the first material layer, a band gap of the source and drain patterns greater than a band gap of a first material layer.
    Type: Application
    Filed: April 15, 2015
    Publication date: August 6, 2015
    Inventors: Hyuk-soon CHOI, Jung-hee LEE, Jai-kwang SHIN, Jae-joon OH, Jong-bong HA, Jong-seob KIM, In-jun HWANG, Ki-ha HONG, Ki-sik IM, Ki-won KIM, Dong-seok KIM
  • Patent number: 9035319
    Abstract: The present disclosure relates to nitride semiconductor and a fabricating method thereof, and a nitride semiconductor according to an exemplary embodiment of the present disclosure includes a nitride based first and second electrode placed with a distance on a substrate, a nitride based channel layer which connects the first and second electrode, an insulating layer which covers the channel layer, and a third electrode which is formed to cover the insulating layer on the insulating layer.
    Type: Grant
    Filed: August 15, 2013
    Date of Patent: May 19, 2015
    Assignee: KYUNGPOOK NATIONAL UNIVERSITY INDUSTRY-ACADEMIC COOPERATION FOUNDATION
    Inventors: Jung-hee Lee, Ki-sik Im, Dong-seok Kim, Hee-sung Kang, Dong-hyeok Son
  • Patent number: 8815688
    Abstract: A method of manufacturing a power device includes forming a first drift region on a substrate. A trench is formed by patterning the first drift region. A second drift region is formed by growing n-gallium nitride (GaN) in the trench, and alternately disposing the first drift region and the second drift region. A source electrode contact layer is formed on the second drift region. A source electrode and a gate electrode are formed on the source electrode contact layer. A drain electrode is formed on one side of the substrate which is an opposite side of the first drift region.
    Type: Grant
    Filed: July 17, 2012
    Date of Patent: August 26, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jae Hoon Lee, Ki Se Kim, Jung Hee Lee, Ki Sik Im, Dong Seok Kim
  • Publication number: 20140103352
    Abstract: The present disclosure relates to nitride semiconductor and a fabricating method thereof, and a nitride semiconductor according to an exemplary embodiment of the present disclosure includes a nitride based first and second electrode placed with a distance on a substrate, a nitride based channel layer which connects the first and second electrode, an insulating layer which covers the channel layer, and a third electrode which is formed to cover the insulating layer on the insulating layer.
    Type: Application
    Filed: August 15, 2013
    Publication date: April 17, 2014
    Applicant: Kyungpook National University Industry-Academic Cooperation Foundation
    Inventors: Jung-hee LEE, Ki-sik IM, Dong-seok KIM, Hee-sung KANG, Dong-hyeok SON
  • Patent number: 8551821
    Abstract: The present invention relates to an enhancement normally off nitride semiconductor device and a method of manufacturing the same. The method includes the steps of: forming a buffer layer on a substrate; forming a first nitride semiconductor layer on the buffer layer; forming a second nitride semiconductor layer on the first nitride semiconductor layer; etching a gate region above the second nitride semiconductor layer up to a predetermined depth of the first nitride semiconductor layer; forming an insulating film on the etched region and the second nitride semiconductor layer; patterning a source/drain region, etching the insulating film in the source/drain region, and forming electrodes in the source/drain region; and forming a gate electrode on the insulating film in the gate region. In this manner, the present invention provides a method of easily implementing a normally off enhancement semiconductor device by originally blocking 2DEG which is generated under a gate region.
    Type: Grant
    Filed: December 4, 2010
    Date of Patent: October 8, 2013
    Assignee: Kyungpook National University Industry-Academic Cooperation Foundation
    Inventors: Jung Hee Lee, Ki Sik Im, Jong Bong Ha
  • Publication number: 20130034939
    Abstract: A method of manufacturing a power device includes forming a first drift region on a substrate. A trench is formed by patterning the first drift region. A second drift region is formed by growing n-gallium nitride (GaN) in the trench, and alternately disposing the first drift region and the second drift region. A source electrode contact layer is formed on the second drift region. A source electrode and a gate electrode are formed on the source electrode contact layer. A drain electrode is formed on one side of the substrate which is an opposite side of the first drift region.
    Type: Application
    Filed: July 17, 2012
    Publication date: February 7, 2013
    Inventors: Jae Hoon LEE, Ki Se KIM, Jung Hee LEE, Ki Sik IM, Dong Seok KIM
  • Publication number: 20120088341
    Abstract: The methods may include forming a first material layer on a substrate, increasing electric resistance of the first material layer, and forming a source pattern and a drain pattern, which are spaced apart from each other, on the first material layer, a band gap of the source and drain patterns greater than a band gap of a first material layer.
    Type: Application
    Filed: July 8, 2011
    Publication date: April 12, 2012
    Applicants: Kyungpook National University Industry-Academic Cooperation Foundation, SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Hyuk-soon Choi, Jung-hee Lee, Jai-kwang Shin, Jae-joon Oh, Jong-bong Ha, Jong-seob Kim, In-jun Hwang, Ki-ha Hong, Ki-sik Im, Ki-won Kim, Dong-seok Kim
  • Patent number: 7973347
    Abstract: Disclosed is a method of fabricating a CMOS (Complementary Metal Oxide Silicon) image sensor. The method includes the steps of: forming a device protective layer and a metal interconnection on a substrate formed with a light receiving device; forming an inner micro-lens on the metal interconnection; coating an interlayer dielectric layer on the inner micro-lens and then forming a color filter; and forming an outer micro-lens including a planarization layer and photoresist on the color filter. The inner micro-lens is formed by depositing the outer layer on dome-shaped photoresist. The curvature radius of the inner micro-lens is precisely and uniformly maintained and the inner micro-lens is easily formed while improving the light efficiency. Since the fabrication process for the CMOS image sensor is simplified, the product yield is improved and the manufacturing cost is reduced.
    Type: Grant
    Filed: January 29, 2010
    Date of Patent: July 5, 2011
    Assignee: Dongbu Electronics Co., Ltd.
    Inventor: Ki Sik Im
  • Publication number: 20110140121
    Abstract: The present invention relates to an enhancement normally off nitride semiconductor device and a method of manufacturing the same. The method includes the steps of: forming a buffer layer on a substrate; forming a first nitride semiconductor layer on the buffer layer; forming a second nitride semiconductor layer on the first nitride semiconductor layer; etching a gate region above the second nitride semiconductor layer up to a predetermined depth of the first nitride semiconductor layer; forming an insulating film on the etched region and the second nitride semiconductor layer; patterning a source/drain region, etching the insulating film in the source/drain region, and forming electrodes in the source/drain region; and forming a gate electrode on the insulating film in the gate region. In this manner, the present invention provides a method of easily implementing a normally off enhancement semiconductor device by originally blocking 2DEG which is generated under a gate region.
    Type: Application
    Filed: December 4, 2010
    Publication date: June 16, 2011
    Applicant: Kyungpook National University Industry Academic Cooperation Foundation
    Inventors: JUNG HEE LEE, Ki Sik Im, Jong Bong Ha
  • Patent number: 7935551
    Abstract: A method for manufacturing a sensor image may include forming a pixel array including a photodiode structure and an insulating film structure in an active area of a semiconductor substrate; forming a metal pad on the insulating film structure; forming a dielectric and/or etch stop film on the metal pad (and optionally over the pixel array); forming a protective layer on the dielectric and/or etch stop film; and forming a pad opening and a pixel opening by etching the protective layer.
    Type: Grant
    Filed: November 30, 2007
    Date of Patent: May 3, 2011
    Assignee: Dongbu HiTek Co., Ltd.
    Inventors: Ki Sik Im, Woo Seok Hyun
  • Publication number: 20100133421
    Abstract: Disclosed is a method of fabricating a CMOS (Complementary Metal Oxide Silicon) image sensor. The method includes the steps of: forming a device protective layer and a metal interconnection on a substrate formed with a light receiving device; forming an inner micro-lens on the metal interconnection; coating an interlayer dielectric layer on the inner micro-lens and then forming a color filter; and forming an outer micro-lens including a planarization layer and photoresist on the color filter. The inner micro-lens is formed by depositing the outer layer on dome-shaped photoresist. The curvature radius of the inner micro-lens is precisely and uniformly maintained and the inner micro-lens is easily formed while improving the light efficiency. Since the fabrication process for the CMOS image sensor is simplified, the product yield is improved and the manufacturing cost is reduced.
    Type: Application
    Filed: January 29, 2010
    Publication date: June 3, 2010
    Inventor: Ki Sik IM
  • Patent number: 7670868
    Abstract: Disclosed is a method of fabricating a CMOS (Complementary Metal Oxide Silicon) image sensor. The method includes the steps of: forming a device protective layer and a metal interconnection on a substrate formed with a light receiving device; forming an inner micro-lens on the metal interconnection; coating an interlayer dielectric layer on the inner micro-lens and then forming a color filter; and forming an outer micro-lens including a planarization layer and photoresist on the color filter. The inner micro-lens is formed by depositing the outer layer on dome-shaped photoresist. The curvature radius of the inner micro-lens is precisely and uniformly maintained and the inner micro-lens is easily formed while improving the light efficiency. Since the fabrication process for the CMOS image sensor is simplified, the product yield is improved and the manufacturing cost is reduced.
    Type: Grant
    Filed: December 27, 2006
    Date of Patent: March 2, 2010
    Assignee: Dongbu Electronics Co., Ltd.
    Inventor: Ki Sik Im
  • Publication number: 20080164499
    Abstract: A method of a CMOS image sensor is disclosed. A method of manufacturing a CMOS image sensor includes forming an epi layer formed over a semiconductor substrate including a pixel region and a peripheral region. At least one oxide film may be formed over the epi layer, including the peripheral region and an upper pad formed therein. A nitride film may be formed over the oxide film. A primary array etching process may be performed with respect to the nitride film using a first photoresist pattern for opening a main pixel region in the pixel region. A secondary array etching process may be performed with respect to the nitride film and the oxide film using a second photoresist pattern for opening the upper pad. The oxide film of the pixel region may be obliquely removed to a predetermined depth. A plurality of color filters and a plurality of micro lenses may be formed over the pixel region after the secondary array etching process.
    Type: Application
    Filed: December 21, 2007
    Publication date: July 10, 2008
    Inventors: Ki-Sik Im, Woo Seok Hyun
  • Publication number: 20080150060
    Abstract: A method for manufacturing a sensor image may include forming a pixel array including a photodiode structure and an insulating film structure in an active area of a semiconductor substrate; forming a metal pad on the insulating film structure; forming a dielectric and/or etch stop film on the metal pad (and optionally over the pixel array); forming a protective layer on the dielectric and/or etch stop film; and forming a pad opening and a pixel opening by etching the protective layer.
    Type: Application
    Filed: November 30, 2007
    Publication date: June 26, 2008
    Inventors: Ki Sik Im, Woo Seok Hyun
  • Publication number: 20070152246
    Abstract: Disclosed is a method of fabricating a CMOS (Complementary Metal Oxide Silicon) image sensor. The method includes the steps of: forming a device protective layer and a metal interconnection on a substrate formed with a light receiving device; forming an inner micro-lens on the metal interconnection; coating an interlayer dielectric layer on the inner micro-lens and then forming a color filter; and forming an outer micro-lens including a planarization layer and photoresist on the color filter. The inner micro-lens is formed by depositing the outer layer on dome-shaped photoresist. The curvature radius of the inner micro-lens is precisely and uniformly maintained and the inner micro-lens is easily formed while improving the light efficiency. Since the fabrication process for the CMOS image sensor is simplified, the product yield is improved and the manufacturing cost is reduced.
    Type: Application
    Filed: December 27, 2006
    Publication date: July 5, 2007
    Inventor: Ki Sik Im