Abstract: A semiconductor device includes an error check execution signal generation circuit configured to generate an error check execution signal for performing an error check operation when an ECS (Error Check and Scrub) command that is generated based on a refresh command is input; and an ECS control circuit configured to generate an ECS active command and an ECS read command for performing the error check operation based on the ECS command and the error check execution signal, and successively generate the ECS read commands to perform the error check operation.

Abstract: Disclosed herein are a method for machine-learning parallelization using host CPUs of a multi-socket structure and an apparatus therefor. The method, performed by the apparatus for machine-learning parallelization using host CPUs of a multi-socket structure, includes a compile phase in which a learning model is split at a layer level for respective pipeline stages and allocated to Non-Uniform Memory Access (NUMA) nodes for respective CPU sockets and a runtime phase in which parameters required for learning are initialized and multiple threads generated in consideration of a policy of each parallelism algorithm are executed by being allocated to respective cores included in the NUMA node.

Abstract: Disclosed herein is a method for distributed training of an AI model in a channel-sharing network environment. The method includes determining whether data parallel processing is applied, calculating a computation time and a communication time when input data is evenly distributed across multiple computation devices, and unevenly distributing the input data across the multiple computation devices based on the computation time and the communication time.

Abstract: A processing-in-memory (PIM) device includes an ECC logic circuit configured to generate first write data, first write parity, second write data, and second write parity from first write input data and second write input data when a write operation in an operation mode is performed, and generate first converted data and second converted data from first read data, first read parity, second read data, and second read parity when a read operation in the operation mode is performed; and a MAC operator configured to perform a MAC arithmetic operation for the first converted data and the second converted data to generate MAC operation result data.

Abstract: Disclosed herein a disaggregation computing system. The disaggregation computing system comprising: a local computing device that comprises a local processor, a local memory bus, a local memory and a local disaggregation controller; a remote computing device that comprises a remote processor, a remote memory bus, a remote memory and a remote disaggregation controller; and a disaggregation network that connects the local computing device and the remote computing device, wherein the local disaggregation controller and the remote disaggregation controller are configured to: check a response delay for access of the remote memory, and control the access of the remote memory based on the response delay.

Abstract: Provided are a hybrid supported catalyst which includes two or more kinds of transition metal compounds having the following Chemical Formulas 1 and 2, thereby preparing a polyolefin, particularly, a high-density polyethylene having a molecular structure which is optimized to improve tensile strength of a chlorinated polyolefin compound, and a method of preparing a polyolefin using the same: wherein all the variables are described herein.

Abstract: An embodiment structural battery for a vehicle includes a positive electrode layer including a first carbon fiber current collecting layer and a positive electrode active material sequentially stacked from top to bottom, a negative electrode layer under the positive electrode layer and including a negative electrode active material and a second carbon fiber current collecting layer sequentially stacked from the top to bottom, upper and lower structure reinforcement layers stacked as outermost upper and lower layers above and below the positive and negative electrode layers, respectively, and solid electrolytes coating a boundary between the positive and negative electrode active materials and coating side surfaces of the positive electrode layer and the negative electrode layer, wherein the structural battery is formed by electrical connection between a positive electrode terminal connected to the positive electrode layer and a negative electrode terminal connected to the negative electrode layer.

Abstract: Proposed is a collision load distribution structure of a fuselage, wherein the structure includes a support unit positioned between a front unit and a rear unit of the fuselage and configured to allow a collision load of the fuselage to be transferred by being connected to the front unit and the rear unit, a wing unit positioned at the inside of the support unit and connected to the support unit to transfer the collision load of the fuselage, and a seat unit coupled to a connection frame mounted in a second-row passenger space of a floor frame constituting the front unit and fastened to a first rear frame extending in a height direction from the floor frame toward the support unit.

Abstract: A semiconductor device includes a programming control signal generation circuit configured to generate a programming control signal and a programming termination signal based on programming data when a programming operation is performed, and a programming control circuit configured to program a command, an address, and an operation signal, based on the programming control signal to generate a programming command, a programming address, and a programming operation signal.

Abstract: A processing-in-memory (PIM) device includes a plurality of memory banks and a plurality of multiplication and accumulation (MAC) operators. The plurality of memory banks include a plurality of even memory banks and a plurality of odd memory banks. The plurality of MAC operators include a first MAC operator configured to be shared by a first even memory bank among the plurality of even memory banks and a first odd memory bank among the plurality of odd memory banks. The first MAC operator is configured to alternately perform an even MAC operation and an odd MAC operation.

Abstract: A semiconductor device includes an information update control circuit configured to generate a self-read pulse for a self-read operation, a self-write pulse for a self-write operation, and an information update section signal that is activated during an information update section when an active operation is performed, and a column control circuit configured to receive the self-read pulse and the self-write pulse, to generate a read column strobe pulse for outputting data or selection information data stored in a core circuit when the self-read operation is performed based on the self-read pulse or the read operation is performed according to the read pulse, and to generate a write column strobe pulse for storing the data or the selection information data in the core circuit when the self-write operation is performed based on the self-write pulse or the write operation is performed according to the write pulse.

Abstract: A processing-in-memory (PIM) system includes a host including an identification (ID)-channel mapper configured to generate a channel address corresponding to an identification received from outside the PIM system, and a plurality of PIM controllers coupled to the host through a plurality of channels, and the plurality of PIM devices coupled to the plurality of PIM controllers through the plurality of channels.

Abstract: A processing-in-memory (PIM) device includes a processing-in-memory (PIM) device includes a memory bank including a left memory bank and a right memory bank, a first global buffer, a second global buffer, a left multiplying-and-accumulating (MAC) operator configured to perform a MAC operation on a first set of a plurality of weight data and a first set of a plurality of vector data, a right MAC operator configured to perform the MAC operation on a second set of the plurality of the weight data and a second set of the plurality of the vector data, and a bias data converter configured to receive bias input data and output bias output data, wherein the bias output data includes a range of numbers that is increased over a range of numbers of the bias input data and includes a value equal to half the value of the bias input data.

Abstract: Disclosed herein a disaggregation computing system. The disaggregation computing system comprising: a local computing device that comprises a local processor, a local memory bus, a local memory and a local disaggregation controller; a remote computing device that comprises a remote processor, a remote memory bus, a remote memory and a remote disaggregation controller; and a disaggregation network that connects the local computing device and the remote computing device, wherein the local disaggregation controller and the remote disaggregation controller are configured to: check a response delay for access of the remote memory, and control the access of the remote memory based on the response delay.

Abstract: A semiconductor manufacturing equipment may include a process chamber for treating a substrate; a front-end module including a first transfer robot, wherein the first transfer robot may be configured to transport the substrate received in a container; a transfer chamber between the front-end module and the process chamber, wherein the transfer chamber may be configured to load or unload the substrate into or out of the process chamber; and a cassette capable of receiving a replaceable component capable of being used in the process chamber. The front-end module may include a seat plate configured to move in a sliding manner so as to retract or extend into or from the front-end module. The cassette may be configured to be loaded into the front-end module while the cassette is seated on the seat plate.

Abstract: A semiconductor device includes a self-test circuit configured to generate an internal clock having a higher frequency than a clock applied from a device external to the semiconductor device, to generate an instruction signal from a pre-instruction signal extracted through a data line, and to generate an internal control signal from the instruction signal. The semiconductor device also includes a command control circuit configured to generate a test command to perform a self-test for determining whether a defect has occurred in first memory cells and second memory cells based on the internal clock and the internal control signal. The semiconductor device further includes a data control circuit configured to output data stored in the first memory cells based on the test command, and to store data output from the first memory cells in the second memory cells.

Abstract: A shift array circuit generates output data having the number of bits greater than the number of bits of target data by shifting the target data by a bit corresponding to a value of shift data. The shift array circuit includes a plurality of shift arrays. The plurality of shift arrays is configured to receive bits of the shift data for each bit and each configured to perform a shift operation on input data that is input to each of the plurality of shift arrays by a shift bit corresponding to an input bit, among the bits of the shift data.

Abstract: An arithmetic device includes a function storage circuit and an activation function (AF) circuit. The function storage circuit stores and outputs a function selection signal, a first function information signal, and a second function information signal. The AF circuit generates an activation function result data by applying a slope value and a maximum value to a multiplication/accumulation (MAC) result data in a function setting mode that is activated by the function selection signal. The slope value is set based on the first function information signal, and the maximum value is set based on the second function information signal.

Abstract: A method and an apparatus for real-time analysis of the district heating network is disclosed. According to an embodiment of the present disclosure, a method for analyzing a district heating network including pipes and fluids inside the pipes includes receiving, by a processor, pipe data representing a structure of the pipes; receiving, by the processor, input data on at least one of the physical state of the district heating network and the flow of fluids; calculating, by the processor, data for at least one of the physical state of the district heating network or the flow of fluids using the pipe data and the input data.

Abstract: An image signal processor includes a register and a disparity correction unit. The register stores disparity data obtained from a pattern image data that an image senor generates, and the image sensor includes a plurality of pixels, and each of the pixel includes at least a first photoelectric conversion element and a second photoelectric conversion element. The image sensor generates the pattern image data in response to a pattern image located at a first distance from the image sensor. The disparity correction unit corrects a disparity distortion of an image data based on the disparity data to generate a result image data, and the image senor generates the image data by capturing an object.