Patents by Inventor Kiarash Bazargan
Kiarash Bazargan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11475288Abstract: Various implementations of sorting networks are described that utilize time-encoded data signals having encoded values. In some examples, an electrical circuit device includes a sorting network configured to receive a plurality of time-encoded signals. Each time-encoded signal of the plurality of time-encoded signals encodes a data value based on a duty cycle of the respective time-encoded signal or based on a proportion of data bits in the respective time-encoded signal that are high relative to the total data bits in the respective time-encoded signal. The sorting network is also configured to sort the plurality of time-encoded signals based on the encoded data values of the plurality of time-encoded signals.Type: GrantFiled: November 5, 2019Date of Patent: October 18, 2022Assignee: Regents of the University of MinnesotaInventors: Mohammadhassan Najafi, David J. Lilja, Marcus Riedel, Kiarash Bazargan
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Patent number: 11275563Abstract: Example devices are described that include a computational unit configured to process first set of data bits encoding a first numerical value and a second set of data bits encoding a second numerical value. The computational unit includes a bit-stream generator configured to generate bit combinations representing first and second bit sequences that encode the first and second numerical values, respectively, based on a proportion of the data bits in the sequence that are high relative to the total data bits. The first bit sequence is generated using a first Sobol sequence source, and the second bit sequence is generated using a second Sobol sequence source different from the first Sobol sequence source. The device also includes computation logic configured to perform a computational operation on the bit combinations and produce an output bit-stream having a set of data bits indicating a result of the computational operation.Type: GrantFiled: June 19, 2020Date of Patent: March 15, 2022Assignee: Regents of the University of MinnesotaInventors: Mohammadhassan Najafi, David J. Lilja, Marcus Riedel, Kiarash Bazargan, Sayed Abdolrasoul Faraji, Bingzhe Li
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Publication number: 20210374507Abstract: Disclosed herein is a low-cost, high-performance, and energy-efficient near-sensor convolution engine based on pulsed unary processing. The disclosed engine removes the necessity of using costly analog-to-digital converters. Synthesis results show that the proposed pulse-based design significantly improves the hardware cost and energy consumption compared to the conventional fixed-point binary and also to the stochastic computing-based designs.Type: ApplicationFiled: May 27, 2021Publication date: December 2, 2021Applicant: University of Louisiana at LafayetteInventors: Mohammad Hassan Najafi, S. Rasoul Faraji, Kiarash Bazargan, David Lilja
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Patent number: 11018689Abstract: In some examples, a device includes shuffling circuitry configured to receive an input unary bit stream and generate a shuffled bit stream by selecting n-tuple combinations of bits of the input unary bit stream. The device also includes stochastic logic circuitry having a plurality of stochastic computational units configured to perform operations on the shuffled bit stream in parallel to produce an output unary bit stream, each of the stochastic computational units operating on a different one of the n-tuple combinations of the bits.Type: GrantFiled: October 19, 2018Date of Patent: May 25, 2021Assignee: Regents of the University of MinnesotaInventors: Soheil Mohajer, Zhiheng Wang, Kiarash Bazargan, Marcus Riedel, David J. Lilja, Sayed Abdolrasoul Faraji
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Publication number: 20200401376Abstract: Example devices are described that include a computational unit configured to process first set of data bits encoding a first numerical value and a second set of data bits encoding a second numerical value. The computational unit includes a bit-stream generator configured to generate bit combinations representing first and second bit sequences that encode the first and second numerical values, respectively, based on a proportion of the data bits in the sequence that are high relative to the total data bits. The first bit sequence is generated using a first Sobol sequence source, and the second bit sequence is generated using a second Sobol sequence source different from the first Sobol sequence source. The device also includes computation logic configured to perform a computational operation on the bit combinations and produce an output bit-stream having a set of data bits indicating a result of the computational operation.Type: ApplicationFiled: June 19, 2020Publication date: December 24, 2020Inventors: Mohammadhassan Najafi, David J. Lilja, Marcus Riedel, Kiarash Bazargan, Sayed Abdolrasoul Faraji, Bingzhe Li
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Patent number: 10763890Abstract: This disclosure describes techniques for performing computational operations on input unary bit streams using one or more scaling networks. In some examples, a device is configured to perform a digital computational operation, where the device includes a plurality of input wires and a plurality of output wires. Each input wire is configured to receive a respective input bit of an encoded input value, and each output wire is configured to output a respective output bit of an encoded output value. The device also includes scaling network circuitry configured to apply a function to the encoded input value by electrically routing at least one input wire of the plurality of input wires to at least two output wires of the plurality of output wires. The device can also include hybrid binary/unary computations.Type: GrantFiled: November 9, 2018Date of Patent: September 1, 2020Assignee: Regents of University of MinnesotaInventors: Soheil Mohajer, Zhiheng Wang, Kiarash Bazargan, Sayed Abdolrasoul Faraji
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Patent number: 10740686Abstract: Devices and techniques are described in which stochastic computation is performed on analog periodic pulse signals instead of random, stochastic digital bit streams. Exploiting pulse width modulation (PWM), time-encoded signals corresponding to specific values are generated by adjusting the frequency (period) and duty cycles of PWM signals. With this approach, the latency, area, and energy consumption are all greatly reduced, as compared to prior stochastic approaches. Circuits synthesized with the proposed approach can work as fast and energy efficiently as a conventional binary design while retaining the fault-tolerance and low-cost advantages of conventional stochastic designs.Type: GrantFiled: January 12, 2018Date of Patent: August 11, 2020Assignee: Regents of the University of MinnesotaInventors: Mohammadhassan Najafi, Shiva Jamalizavareh, David J. Lilja, Marcus Riedel, Kiarash Bazargan, Ramesh Harjani
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Publication number: 20200143234Abstract: Various implementations of sorting networks are described that utilize time-encoded data signals having encoded values. In some examples, an electrical circuit device includes a sorting network configured to receive a plurality of time-encoded signals. Each time-encoded signal of the plurality of time-encoded signals encodes a data value based on a duty cycle of the respective time-encoded signal or based on a proportion of data bits in the respective time-encoded signal that are high relative to the total data bits in the respective time-encoded signal. The sorting network is also configured to sort the plurality of time-encoded signals based on the encoded data values of the plurality of time-encoded signals.Type: ApplicationFiled: November 5, 2019Publication date: May 7, 2020Inventors: Mohammadhassan Najafi, David J. Lilja, Marcus Riedel, Kiarash Bazargan
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Patent number: 10520975Abstract: In some examples, a device includes an integrated circuit and two or more computational units configured to process respective stochastic bit streams in accordance with respective input clocks. Each of the stochastic bit streams comprises sequential sets of data bits, each of the sets of data bits representing a numerical value based on a probability that any bit in the respective set of data bits is one. The respective input clocks for each of the two or more computational units are unsynchronized.Type: GrantFiled: March 3, 2017Date of Patent: December 31, 2019Assignee: Regents of the University of MinnesotaInventors: David J. Lilja, Mohammadhassan Najafi, Marcus Riedel, Kiarash Bazargan
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Publication number: 20190149166Abstract: This disclosure describes techniques for performing computational operations on input unary bit streams using one or more scaling networks. In some examples, a device is configured to perform a digital computational operation, where the device includes a plurality of input wires and a plurality of output wires. Each input wire is configured to receive a respective input bit of an encoded input value, and each output wire is configured to output a respective output bit of an encoded output value. The device also includes scaling network circuitry configured to apply a function to the encoded input value by electrically routing at least one input wire of the plurality of input wires to at least two output wires of the plurality of output wires. The device can also include hybrid binary/unary computations.Type: ApplicationFiled: November 9, 2018Publication date: May 16, 2019Inventors: Soheil Mohajer, Zhiheng Wang, Kiarash Bazargan, Sayed Abdolrasoul Faraji
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Publication number: 20190121839Abstract: In some examples, a device includes shuffling circuitry configured to receive an input unary bit stream and generate a shuffled bit stream by selecting n-tuple combinations of bits of the input unary bit stream. The device also includes stochastic logic circuitry having a plurality of stochastic computational units configured to perform operations on the shuffled bit stream in parallel to produce an output unary bit stream, each of the stochastic computational units operating on a different one of the n-tuple combinations of the bits.Type: ApplicationFiled: October 19, 2018Publication date: April 25, 2019Inventors: Soheil Mohajer, Zhiheng Wang, Kiarash Bazargan, Marcus Riedel, David J. Lilja, Sayed Abdolrasoul Faraji
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Publication number: 20180204131Abstract: Devices and techniques are described in which stochastic computation is performed on analog periodic pulse signals instead of random, stochastic digital bit streams. Exploiting pulse width modulation (PWM), time-encoded signals corresponding to specific values are generated by adjusting the frequency (period) and duty cycles of PWM signals. With this approach, the latency, area, and energy consumption are all greatly reduced, as compared to prior stochastic approaches. Circuits synthesized with the proposed approach can work as fast and energy efficiently as a conventional binary design while retaining the fault-tolerance and low-cost advantages of conventional stochastic designs.Type: ApplicationFiled: January 12, 2018Publication date: July 19, 2018Inventors: Mohammadhassan Najafi, Shiva Jamalizavareh, David J. Lilja, Marcus Riedel, Kiarash Bazargan, Ramesh Harjani
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Publication number: 20170255225Abstract: In some examples, a device includes an integrated circuit and two or more computational units configured to process respective stochastic bit streams in accordance with respective input clocks. Each of the stochastic bit streams comprises sequential sets of data bits, each of the sets of data bits representing a numerical value based on a probability that any bit in the respective set of data bits is one. The respective input clocks for each of the two or more computational units are unsynchronized.Type: ApplicationFiled: March 3, 2017Publication date: September 7, 2017Inventors: David J. Lilja, Mohammadhassan Najafi, Marcus Riedel, Kiarash Bazargan