Abstract: An electronic device includes a first sample circuit configured to generate a first sampling signal by sampling an input signal in response to edges of a clock signal, a first comparator configured to generate a first logic decision signal by comparing a voltage level of the first sampling signal with a reference voltage level, an analog bang-bang phase detector configured to generate a first detection signal by executing an exclusive OR (XOR) operation on successive samples of the first logic decision signal, and a digitally controlled oscillator configured to vary a frequency of the clock signal according to the first detection signal.

Abstract: A low drop-out (LDO) linear regulator includes: a pass transistor coupled between an input terminal and an output terminal; an error amplifier suitable for amplifying and outputting a difference between a feedback voltage corresponding to an output voltage of the output terminal and a predetermined reference voltage; a buffer including an input terminal which is coupled to an output node of the error amplifier and an output terminal which is coupled to a gate of the pass transistor; a first compensation circuit suitable for driving an equivalent resistance of the output node of the error amplifier to be in inverse proportion to a load current; and a second compensation circuit suitable for driving an equivalent resistance of an output node of the buffer to be in inverse proportion to the load current.

Abstract: A low drop-out (LDO) linear regulator includes: a pass transistor coupled between an input terminal and an output terminal; an error amplifier suitable for amplifying and outputting a difference between a feedback voltage corresponding to an output voltage of the output terminal and a predetermined reference voltage; a buffer including an input terminal which is coupled to an output node of the error amplifier and an output terminal which is coupled to a gate of the pass transistor; a first compensation circuit suitable for driving an equivalent resistance of the output node of the error amplifier to be in inverse proportion to a load current; and a second compensation circuit suitable for driving an equivalent resistance of an output node of the buffer to be in inverse proportion to the load current.