Patents by Inventor Kiichiro TAKENAKA

Kiichiro TAKENAKA has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11916520
    Abstract: A Doherty amplifier including a main amplifier and a peak amplifier is mounted on a package substrate. A low noise amplifier is further mounted on the package substrate. A transmit/receive switch switches in terms of time between a transmission connection state in which an output signal of the Doherty amplifier is supplied to an antenna and a reception connection state in which a signal received by the antenna is inputted to the low noise amplifier.
    Type: Grant
    Filed: June 3, 2022
    Date of Patent: February 27, 2024
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventors: Satoshi Tanaka, Kiichiro Takenaka, Satoshi Arayashiki, Satoshi Sakurai
  • Patent number: 11856525
    Abstract: A high-frequency signal processing apparatus and a wireless communication apparatus can achieve a decrease in power consumption. For example, when an indicated power level to a high-frequency power amplifier is equal to or greater than a second reference value, envelope tracking is performed by causing a source voltage control circuit to control a high-speed DCDC converter using a detection result of an envelope detecting circuit and causing a bias control circuit to indicate a fixed bias value. The source voltage control circuit and the bias control circuit indicate a source voltage and a bias value decreasing in proportion to a decrease in the indicated power level when the indicated power level is in a range of the second reference value to the first reference value, and indicate a fixed source voltage and a fixed bias value when the indicated power level is less than the first reference value.
    Type: Grant
    Filed: May 2, 2023
    Date of Patent: December 26, 2023
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventors: Satoshi Tanaka, Kiichiro Takenaka, Takayuki Tsutsui, Taizo Yamawaki, Shun Imai
  • Patent number: 11791782
    Abstract: A semiconductor chip includes a plurality of transistor rows. Corresponding to the plurality of transistor rows, a first bump connected to a collector of the transistor is arranged, and a second bump connected to an emitter is arranged. The transistor rows are arranged along sides of a convex polygon. A first land and a second land provided in a circuit board are connected to the first bump and the second bump, respectively. A first impedance conversion circuit connects the first land and the signal output terminal. A plurality of transistors in the transistor row are grouped into a plurality of groups, and the first impedance conversion circuit includes a reactance element arranged for each of the groups.
    Type: Grant
    Filed: December 16, 2020
    Date of Patent: October 17, 2023
    Assignee: Murata Manufacturing Co., Ltd.
    Inventors: Masao Kondo, Kiichiro Takenaka, Satoshi Tanaka, Takayuki Tsutsui
  • Publication number: 20230276372
    Abstract: A high-frequency signal processing apparatus and a wireless communication apparatus can achieve a decrease in power consumption. For example, when an indicated power level to a high-frequency power amplifier is equal to or greater than a second reference value, envelope tracking is performed by causing a source voltage control circuit to control a high-speed DCDC converter using a detection result of an envelope detecting circuit and causing a bias control circuit to indicate a fixed bias value. The source voltage control circuit and the bias control circuit indicate a source voltage and a bias value decreasing in proportion to a decrease in the indicated power level when the indicated power level is in a range of the second reference value to the first reference value, and indicate a fixed source voltage and a fixed bias value when the indicated power level is less than the first reference value.
    Type: Application
    Filed: May 2, 2023
    Publication date: August 31, 2023
    Inventors: Satoshi TANAKA, Kiichiro TAKENAKA, Takayuki TSUTSUI, Taizo YAMAWAKI, Shun IMAI
  • Publication number: 20230199671
    Abstract: A high-frequency signal processing apparatus and a wireless communication apparatus can achieve a decrease in power consumption. For example, when an indicated power level to a high-frequency power amplifier is equal to or greater than a second reference value, envelope tracking is performed by causing a source voltage control circuit to control a high-speed DCDC converter using a detection result of an envelope detecting circuit and causing a bias control circuit to indicate a fixed bias value. The source voltage control circuit and the bias control circuit indicate a source voltage and a bias value decreasing in proportion to a decrease in the indicated power level when the indicated power level is in a range of the second reference value to the first reference value, and indicate a fixed source voltage and a fixed bias value when the indicated power level is less than the first reference value.
    Type: Application
    Filed: February 21, 2023
    Publication date: June 22, 2023
    Inventors: Satoshi TANAKA, Kiichiro TAKENAKA, Takayuki TSUTSUI, Taizo YAMAWAKI, Shun IMAI
  • Patent number: 11611942
    Abstract: A high-frequency signal processing apparatus and a wireless communication apparatus can achieve a decrease in power consumption. For example, when an indicated power level to a high-frequency power amplifier is equal to or greater than a second reference value, envelope tracking is performed by causing a source voltage control circuit to control a high-speed DCDC converter using a detection result of an envelope detecting circuit and causing a bias control circuit to indicate a fixed bias value. The source voltage control circuit and the bias control circuit indicate a source voltage and a bias value decreasing in proportion to a decrease in the indicated power level when the indicated power level is in a range of the second reference value to the first reference value, and indicate a fixed source voltage and a fixed bias value when the indicated power level is less than the first reference value.
    Type: Grant
    Filed: February 23, 2022
    Date of Patent: March 21, 2023
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventors: Satoshi Tanaka, Kiichiro Takenaka, Takayuki Tsutsui, Taizo Yamawaki, Shun Imai
  • Patent number: 11528012
    Abstract: An active balun circuit includes first and second transistors having emitters electrically coupled to each other and configured to output differential signals and a circuit element coupled between the connection point of the emitter of the first transistor and the emitter of the second transistor and a reference potential. The impedance of the circuit element at a particular frequency of the input signal appears significantly larger than impedances at other frequencies. An input signal from an input terminal is inputted to the base of the first transistor. The reference potential is applied to the base of the second transistor. A supply voltage is applied to the collector of the first transistor and the collector of the second transistor. A signal from the collector of the first transistor and a signal from the collector of the second transistor are outputted as the differential signals.
    Type: Grant
    Filed: November 5, 2020
    Date of Patent: December 13, 2022
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventors: Takayuki Tsutsui, Satoshi Tanaka, Kiichiro Takenaka, Masatoshi Hase
  • Patent number: 11496100
    Abstract: A matching network is a matching network of a power amplifier circuit that outputs a signal obtained by a differential amplifier amplifying power of a high-frequency signal. The matching network includes an input-side winding connected between differential outputs of the differential amplifier; an output-side winding that is coupled to the input-side winding via an electromagnetic field and whose one end is connected to a reference potential; a first LC series resonant circuit including a capacitive element and an inductive element connected in series with each other, and being connected in parallel with the input-side winding; and a second LC series resonant circuit including a capacitive element and an inductive element connected in series with each other, and being connected in parallel with the output-side winding.
    Type: Grant
    Filed: September 3, 2020
    Date of Patent: November 8, 2022
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventors: Kiichiro Takenaka, Masahiro Ito, Tsuyoshi Sato, Kozo Sato, Hidetoshi Matsumoto
  • Publication number: 20220294395
    Abstract: A Doherty amplifier including a main amplifier and a peak amplifier is mounted on a package substrate. A low noise amplifier is further mounted on the package substrate. A transmit/receive switch switches in terms of time between a transmission connection state in which an output signal of the Doherty amplifier is supplied to an antenna and a reception connection state in which a signal received by the antenna is inputted to the low noise amplifier.
    Type: Application
    Filed: June 3, 2022
    Publication date: September 15, 2022
    Inventors: Satoshi TANAKA, Kiichiro TAKENAKA, Satoshi ARAYASHIKI, Satoshi SAKURAI
  • Publication number: 20220256477
    Abstract: A high-frequency signal processing apparatus and a wireless communication apparatus can achieve a decrease in power consumption. For example, when an indicated power level to a high-frequency power amplifier is equal to or greater than a second reference value, envelope tracking is performed by causing a source voltage control circuit to control a high-speed DCDC converter using a detection result of an envelope detecting circuit and causing a bias control circuit to indicate a fixed bias value. The source voltage control circuit and the bias control circuit indicate a source voltage and a bias value decreasing in proportion to a decrease in the indicated power level when the indicated power level is in a range of the second reference value to the first reference value, and indicate a fixed source voltage and a fixed bias value when the indicated power level is less than the first reference value.
    Type: Application
    Filed: February 23, 2022
    Publication date: August 11, 2022
    Inventors: Satoshi TANAKA, Kiichiro TAKENAKA, Takayuki TSUTSUI, Taizo YAMAWAKI, Shun IMAI
  • Patent number: 11394348
    Abstract: A power amplifier circuit includes a first amplifier including two amplifiers connected in series with a matching circuit interposed therebetween, a first power supply circuit that supplies a first power supply voltage to a former amplifier of the first amplifier, and a second power supply circuit that supplies a second power supply voltage to a latter amplifier of the first amplifier.
    Type: Grant
    Filed: April 21, 2020
    Date of Patent: July 19, 2022
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventor: Kiichiro Takenaka
  • Patent number: 11368176
    Abstract: A transmission unit includes: a power amplification module that amplifies the power of an input signal and outputs an amplified signal; and a power supply module that supplies a power supply voltage to the power amplification module on the basis of a first control signal corresponding to the band width of the input signal. On the basis of the first control signal, the power supply module varies the power supply voltage in accordance with the amplitude level of the input signal in the case where the band width of the input signal is a first band width and varies the power supply voltage in accordance with the average output power of the power amplification module in the case where the band width of the input signal is a second band width that is larger than the first band width.
    Type: Grant
    Filed: November 3, 2020
    Date of Patent: June 21, 2022
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventor: Kiichiro Takenaka
  • Patent number: 11356064
    Abstract: A Doherty amplifier including a main amplifier and a peak amplifier is mounted on a package substrate. A low noise amplifier is further mounted on the package substrate. A transmit/receive switch switches in terms of time between a transmission connection state in which an output signal of the Doherty amplifier is supplied to an antenna and a reception connection state in which a signal received by the antenna is inputted to the low noise amplifier.
    Type: Grant
    Filed: May 6, 2020
    Date of Patent: June 7, 2022
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventors: Satoshi Tanaka, Kiichiro Takenaka, Satoshi Arayashiki, Satoshi Sakurai
  • Patent number: 11309844
    Abstract: A power amplifier includes a power splitter that splits a first signal into a second signal and a third signal, a first amplifier that amplifies the second signal within an area where the first signal has a power level greater than or equal to a first level and that outputs a fourth signal, a second amplifier that amplifies the third signal within an area where the first signal has a power level greater than or equal to a second level higher than the first level and that outputs a fifth signal, an output unit that outputs an amplified signal of the first signal, a first and a second LC parallel resonant circuit, and a choke inductor having an end to which a power supply voltage is supplied and another end connected to a node of the first and second LC parallel resonant circuits.
    Type: Grant
    Filed: July 17, 2020
    Date of Patent: April 19, 2022
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventor: Kiichiro Takenaka
  • Patent number: 11290964
    Abstract: A high-frequency signal processing apparatus and a wireless communication apparatus can achieve a decrease in power consumption. For example, when an indicated power level to a high-frequency power amplifier is equal to or greater than a second reference value, envelope tracking is performed by causing a source voltage control circuit to control a high-speed DCDC converter using a detection result of an envelope detecting circuit and causing a bias control circuit to indicate a fixed bias value. The source voltage control circuit and the bias control circuit indicate a source voltage and a bias value decreasing in proportion to a decrease in the indicated power level when the indicated power level is in a range of the second reference value to the first reference value, and indicate a fixed source voltage and a fixed bias value when the indicated power level is less than the first reference value.
    Type: Grant
    Filed: April 13, 2021
    Date of Patent: March 29, 2022
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventors: Satoshi Tanaka, Kiichiro Takenaka, Takayuki Tsutsui, Taizo Yamawaki, Shun Imai
  • Patent number: 11223327
    Abstract: A power amplifier includes a distributor distributing an input first signal to a second signal and a third signal delayed by about 2? degrees (45<?<90) from the second signal, a first amplifier amplifying the second signal and outputting a fourth signal when a first-signal power level is not lower than a first level, a second amplifier amplifying the third signal and outputting a fifth signal when the first-signal power level is not lower than a second level that is greater than the first level, a first phase shifter receiving the fourth signal and outputting a sixth signal delayed by about ? degrees from the fourth signal, a second phase shifter receiving the fifth signal and outputting a seventh signal advanced by about ? degrees from the fifth signal, and a combiner combining the sixth and seventh signals and outputting an amplified signal of the first signal.
    Type: Grant
    Filed: September 10, 2020
    Date of Patent: January 11, 2022
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventor: Kiichiro Takenaka
  • Publication number: 20210305950
    Abstract: A radio frequency signal having a constant amplitude is modulated by a digital modulation signal and a radio frequency input signal whose amplitude changes stepwise is generated. The radio frequency input signal is input into a power amplifier that is an evaluation target. A period in which an amplitude of the radio frequency input signal is constant is defined as a measurement period and an output signal of the power amplifier is measured in each of measurement periods in which amplitudes of the radio frequency input signal are different from each other.
    Type: Application
    Filed: March 23, 2021
    Publication date: September 30, 2021
    Inventors: Kiichiro TAKENAKA, Masahiro ITO, Yuuma NOGUCHI, Daiji NAGASHIMA, Hidetoshi MATSUMOTO
  • Patent number: 11128271
    Abstract: A power supply circuit supplies a variable voltage to a power amplifier that amplifies a radio-frequency signal, and includes a transistor and a current detecting resistor. The transistor includes a collector or drain that is supplied with a fixed voltage from a fixed voltage source, a base or gate that receives an envelope signal tracking an envelope of the radio-frequency signal, and an emitter or source that outputs the variable voltage that is based on the envelope signal. The current detecting resistor is electrically connected between the fixed voltage source and the collector or drain of the transistor.
    Type: Grant
    Filed: December 19, 2019
    Date of Patent: September 21, 2021
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventors: Yuuma Noguchi, Hidetoshi Matsumoto, Kiichiro Takenaka, Satoshi Tanaka
  • Publication number: 20210235392
    Abstract: A high-frequency signal processing apparatus and a wireless communication apparatus can achieve a decrease in power consumption. For example, when an indicated power level to a high-frequency power amplifier is equal to or greater than a second reference value, envelope tracking is performed by causing a source voltage control circuit to control a high-speed DCDC converter using a detection result of an envelope detecting circuit and causing a bias control circuit to indicate a fixed bias value. The source voltage control circuit and the bias control circuit indicate a source voltage and a bias value decreasing in proportion to a decrease in the indicated power level when the indicated power level is in a range of the second reference value to the first reference value, and indicate a fixed source voltage and a fixed bias value when the indicated power level is less than the first reference value.
    Type: Application
    Filed: April 13, 2021
    Publication date: July 29, 2021
    Inventors: Satoshi TANAKA, Kiichiro TAKENAKA, Takayuki TSUTSUI, Taizo YAMAWAKI, Shun IMAI
  • Publication number: 20210194444
    Abstract: A semiconductor chip includes a plurality of transistor rows. Corresponding to the plurality of transistor rows, a first bump connected to a collector of the transistor is arranged, and a second bump connected to an emitter is arranged. The transistor rows are arranged along sides of a convex polygon. A first land and a second land provided in a circuit board are connected to the first bump and the second bump, respectively. A first impedance conversion circuit connects the first land and the signal output terminal. A plurality of transistors in the transistor row are grouped into a plurality of groups, and the first impedance conversion circuit includes a reactance element arranged for each of the groups.
    Type: Application
    Filed: December 16, 2020
    Publication date: June 24, 2021
    Applicant: Murata Manufacturing Co., Ltd.
    Inventors: Masao KONDO, Kiichiro TAKENAKA, Satoshi TANAKA, Takayuki TSUTSUI