Abstract: An electrically alterable non-volatile semiconductor memory device includes a plurality of electrically alterable memory cells arranged in columns and rows, a decoder circuit which selects at least one of the plurality of memory cells and does not select others, a writing circuit for writing a selected data in the selected memory cell through the decoder circuit, a reading circuit for reading a data stored in the selected memory cell through the decoder circuit, a comparing circuit for holding the data stored in the selected memory cell and data to be written in the memory cell and comparing both the data with each other, a judging circuit for judging whether the stored data in the selected memory cell is required to be altered or not on the basis of the comparison result of the comparing circuit, and an alteration control circuit for performing altering of the data of the memory cell when stored data is required to be altered on the basis of the judgment result of the judging circuit.

Abstract: A power supply circuit selectively provides various voltage signals to memory devices, such as EPROM or EEPROM for example. The power supply circuit receives voltage signals at input terminals and selectively outputs a voltage signal, in accordance with the requirement for reading, writing and erasing operations, while preventing leakage current between voltage signals. Among other things, the power supply circuit provides a relatively low impedance and does not require high voltage levels for performing the above memory operations. The selection of voltage signals at an output terminal is effected by control means for controlling conductivity and non-conductivity of MOS transistors based on a control signal supplied from a control signal input terminal.

Abstract: A bootstrap circuit particularly suitable for low voltage applications and use with semiconductor memories is disclosed.

Abstract: An electrically alterable non-volatile semiconductor memory. The memory cells are formed in a matrix of columns and rows. A row decoder and column decoder are provided to select one of the row lines and column lines. Mode selection means are provided for selecting a writing mode, a first erasing mode for erasing a row of memory cells, a second erasing mode for erasing a selected memory cell on a bit basis, and a reading mode for reading the contents of each memory cell. The individual erasing modes reduce the overall power consumption of the device, while permitting block erasing as well as individual cell erasing.

Abstract: The electrically rewritable nonvolatile semiconductor memory device includes a plurality of memory cells arranged in rows and columns, a decoder circuit for selecting at least one of the plurality of memory cells, a writing circuit for writing data in the selected memory cell through the decoder circuit, a reading circuit for reading the data from the selected memory cell, a detecting circuit for detecting a change of the threshold voltage of each of the non-selected memory cells, which change is caused by a voltage applied to the non-selected memory cell when writing the data in the selected memory cell, and a restoring circuit for restoring the threshold voltage of the non-selected memory cell a value equal to or near to its original value on the basis of the result of the above detection.

Abstract: A non-volatile semiconductor memory device capable of electrical programming including a plurality of memory cells, means for selecting at least one memory cell from the plurality of memory cells, mode setting means for setting one of a first read mode in which data written in the selected memory cell is read and a second read mode for detecting a change of the threshold voltage level of the selected memory cell, first comparing means for comparing a voltage signal read from the selected memory cell with at least a predetermined single first reference voltage level when the first read mode is set, first output means for producing a signal indicative of data written in the selected memory cell on the basis of the comparison in the first comparing means, second comparing means for comparing the cell voltage signal with at least a predetermined single second reference voltage level different from the first reference voltage level when the second read mode is set, and second output means for producing a signal in

Abstract: A method of writing or reading at least three different data in each memory cell, in a non-volatile semiconductor memory device having a plurality of memory cells, each memory cell having floating gate for setting a given threshold voltage in the memory cell. In addition, a non-volatile semiconductor memory device capable of checking if the data stored in the selected memory cell is correct by using one of at least two binary bits of the data as a parity bit, and a method of writing or reading data in or from that memory device.

Abstract: An electrically erasable non-volatile semiconductor memory device comprising a plurality of row lines and column lines, a plurality of memory cells connected in a matrix to the plurality of row lines and column lines, a selection circuit for selecting a desired one of the plurality of memory cells, and write-control circuit for writing data into the plurality of memory cells. The write-control circuit is adapted to preset at least four voltage signals having different voltage values, and to select one of four voltage signals according to a data signal externally applied thereto and applying the selected voltage signal to the selected memory cell. Also included is read-control circuit for reading out data written into the selected memory cell and converting the data read-out from the selected memory cell into a data signal corresponding to one of the four voltage signals.

Abstract: A method for writing data to a selected EEPROM memory cell and erasing data in a selected EEPROM memory cell. During writing of the EEPROM memory cell, a tunnel effect is used to draw charges from the charge injection layer of a memory transistor into the drain. A negative voltage lower than ground potential is applied to the control gate of the selected memory cell and the presence or absence of the tunnel effect is controlled by the level of voltage applied to the drain of the selected memory cell. Other memory cells which are not being written with data are maintained free of the tunnel effect by applying a voltage higher than the gate voltage of the selected memory cell, and lower than the threshold voltage of the control gate to the non-selected memory cell with respect to its drain connection. During erasing of a selected memory cell, the power supply voltage for the memory is applied to the control gate of the selected memory cell and the drain and source are grounded.

Abstract: A semiconductor memory device having a self-correcting function comprises memory cells for storing data and memory cells for storing parity bit data. The criterion of detecting in the first read circuit is set smaller and the criterion of detecting in the second read circuit is set greater in value than the current value read in such a state that the electric charge in the memory cell becomes depleted. In this way, the first read circuit detects a current value smaller and the second read circuit detects a current value greater than the value of the current flowing through the memory cell holding the bit error because of charge depletion. Consequently, even if the variation of the threshold resulting from the charge depletion allows the presence of a faulty memory cell, one of the read circuits can make a correct data read.

Abstract: In a nonvolatile memory device or a microcomputer with a nonvolatile memory, data errors arising from loss of charge in the floating gates of memory cells are detected and corrected by applying two different sense voltages to the memory cells and comparing the outputs. Instead of using a cumbersome error-correcting code, this error-correcting scheme requires only one parity bit per word, yet it can detect and correct errors in any odd number of bits. Benefits include reduced chip size and longer life for electrically erasable and programmable memories.