Patents by Inventor Kilho Lee
Kilho Lee has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240114700Abstract: A semiconductor device includes cell lower conductive lines and peripheral lower conductive lines on a substrate, lower electrode contacts on the cell lower conductive lines, peripheral conductive contacts on the peripheral lower conductive lines, variable resistance patterns horizontally spaced apart from each other on the lower electrode contacts. The lower electrode contacts are respectively connected to the variable resistance patterns. Peripheral conductive lines are horizontally spaced apart from the variable resistance patterns on the peripheral conductive contacts. The peripheral conductive contacts are connected to the peripheral conductive lines. The cell and peripheral lower conductive lines are connected to the lower electrode contacts and the peripheral conductive contacts, respectively. The cell and peripheral lower conductive lines are at the same height.Type: ApplicationFiled: August 11, 2023Publication date: April 4, 2024Inventors: Yongjae LEE, Seung Pil KO, Kilho LEE, Jeongjin LEE
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Publication number: 20230217835Abstract: A method of manufacturing a memory device includes sequentially forming a first magnetization layer, a tunnel barrier layer, and a second magnetization layer on each other; forming a magnetic tunnel junction structure by patterning the first magnetization layer, the tunnel barrier layer, and the second magnetization layer; forming a sidewall metal layer by etching a portion of a redeposited metal covering a sidewall of the magnetic tunnel junction structure; performing an oxidizing operation that includes oxidizing an exposed surface of the sidewall metal layer to provide an oxidized sidewall metal layer; and performing an irradiating operation that includes irradiating an ion beam towards the oxidized sidewall metal layer. A sidewall insulating layer covering a sidewall of the magnetic tunnel junction structure is formed by alternately performing the oxidizing operation and the irradiating operation two or more times.Type: ApplicationFiled: December 22, 2022Publication date: July 6, 2023Applicant: Samsung Electronics Co., Ltd.Inventors: Manjin EOM, Gawon LEE, Seungpil KO, Kilho LEE
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Patent number: 11665910Abstract: A magnetic memory device includes a magnetic tunnel junction pattern on a substrate, a first conductive pattern between the substrate and the magnetic tunnel junction pattern, lower contact plugs between the first conductive pattern and the substrate and disposed at respective sides of the magnetic tunnel junction pattern, and second conductive patterns on the lower contact plugs, respectively. The second conductive patterns connect the lower contact plugs to the first conductive pattern. The second conductive patterns include a ferromagnetic material.Type: GrantFiled: December 9, 2021Date of Patent: May 30, 2023Inventors: Kilho Lee, Gwanhyeob Koh
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Patent number: 11659719Abstract: A semiconductor device including a substrate that has a first region and a second region, a plurality of lower conductive patterns on the substrate, the plurality of lower conductive patterns including a first conductive pattern in the first region of the substrate and a second conductive pattern in the second region of the substrate, a magnetic tunnel junction on the first conductive pattern, a contact between the magnetic tunnel junction and the first conductive pattern, a through electrode on the second conductive pattern, and a plurality of upper conductive patterns on the magnetic tunnel junction and the through electrode. The contact includes a first contact on the lower conductive patterns, a second contact on the first contact, and a first barrier layer that covers a bottom surface and a lateral surface of the second contact.Type: GrantFiled: July 21, 2021Date of Patent: May 23, 2023Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Kilho Lee, Gwanhyeob Koh
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Patent number: 11557631Abstract: Disclosed is a semiconductor device including first conductive lines, second conductive lines crossing the first conductive lines, and memory cells at intersections between the first conductive lines and the second conductive lines. Each of the memory cells includes a magnetic tunnel junction pattern, a bi-directional switching pattern connected in series to the magnetic tunnel junction pattern, and a conductive pattern between the magnetic tunnel junction pattern and the bi-directional switching pattern.Type: GrantFiled: November 3, 2020Date of Patent: January 17, 2023Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Kilho Lee, Gwanhyeob Koh, Ilmok Park, Junhee Lim
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Publication number: 20220328083Abstract: A magnetic memory device may include a substrate including a first region and a second region, a first interlayer insulating layer on the substrate, a first capping layer on the first interlayer insulating layer, the first capping layer covering the first and second regions of the substrate, a second interlayer insulating layer on a portion of the first capping layer covering the first region of the substrate, a bottom electrode contact included in the second interlayer insulating layer, a magnetic tunnel junction pattern on the bottom electrode contact, and a second capping layer on the second interlayer insulating layer, the second capping layer being in contact with the first capping layer on the second region of the substrate.Type: ApplicationFiled: November 30, 2021Publication date: October 13, 2022Applicant: Samsung Electronics Co., Ltd.Inventors: Seung Pil KO, Yongjae KIM, Geonhee BAE, Gawon LEE, Kilho LEE
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Patent number: 11437432Abstract: An embedded device includes a first insulation layer, a second insulation layer on the first insulation layer, a lower electrode contact in the first insulation layer in a first region, a first structure, having a lower electrode, a magnetic tunnel junction, and an upper electrode, in the second insulation layer and contacting the lower electrode contact, a first metal wiring structure through the first and second insulation layers in a second region, a third insulation layer on the second insulation layer, a bit line structure through the third insulation layer and the second insulation layer in the first region, the bit line structure having a first height and contacting the upper electrode, and a second metal wiring structure through the third insulation layer in the second region, the second metal wiring structure contacting the first metal wiring structure, and having a second height lower than the first height.Type: GrantFiled: September 22, 2020Date of Patent: September 6, 2022Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Kilho Lee, Gwanhyeob Koh, Woojin Kim
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Patent number: 11361798Abstract: A first memory section is disposed on a substrate. A second memory section is vertically stacked on the first memory section. The first memory section is provided between the substrate and the second memory section. The first memory section includes a flash memory cell structure, and the second memory section includes a variable resistance memory cell structure. The flash memory cell structure includes at least one cell string comprising a plurality of first memory cells connected in series to each other and a bit line on the substrate connected to the at least one cell string. The bit line is interposed vertically between the at least one cell string and the second memory section and connected to the second memory section.Type: GrantFiled: May 13, 2019Date of Patent: June 14, 2022Inventors: Kilho Lee, Gwanhyeob Koh, Junhee Lim, Hongsoo Kim, Chang-hoon Jeon
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Publication number: 20220102426Abstract: A magnetic memory device includes a magnetic tunnel junction pattern on a substrate, a first conductive pattern between the substrate and the magnetic tunnel junction pattern, lower contact plugs between the first conductive pattern and the substrate and disposed at respective sides of the magnetic tunnel junction pattern, and second conductive patterns on the lower contact plugs, respectively. The second conductive patterns connect the lower contact plugs to the first conductive pattern. The second conductive patterns include a ferromagnetic material.Type: ApplicationFiled: December 9, 2021Publication date: March 31, 2022Inventors: Kilho Lee, Gwanhyeob Koh
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Patent number: 11211425Abstract: A magnetic memory device includes a magnetic tunnel junction pattern on a substrate, a first conductive pattern between the substrate and the magnetic tunnel junction pattern, lower contact plugs between the first conductive pattern and the substrate and disposed at respective sides of the magnetic tunnel junction pattern, and second conductive patterns on the lower contact plugs, respectively. The second conductive patterns connect the lower contact plugs to the first conductive pattern. The second conductive patterns include a ferromagnetic material.Type: GrantFiled: June 8, 2020Date of Patent: December 28, 2021Inventors: Kilho Lee, Gwanhyeob Koh
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Publication number: 20210351233Abstract: A semiconductor device including a substrate that has a first region and a second region, a plurality of lower conductive patterns on the substrate, the plurality of lower conductive patterns including a first conductive pattern in the first region of the substrate and a second conductive pattern in the second region of the substrate, a magnetic tunnel junction on the first conductive pattern, a contact between the magnetic tunnel junction and the first conductive pattern, a through electrode on the second conductive pattern, and a plurality of upper conductive patterns on the magnetic tunnel junction and the through electrode. The contact includes a first contact on the lower conductive patterns, a second contact on the first contact, and a first barrier layer that covers a bottom surface and a lateral surface of the second contact.Type: ApplicationFiled: July 21, 2021Publication date: November 11, 2021Applicant: Samsung Electronics Co., Ltd.Inventors: Kilho Lee, Gwanhyeob Koh
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Patent number: 11121175Abstract: A semiconductor device including a substrate that has a first region and a second region, a plurality of lower conductive patterns on the substrate, the plurality of lower conductive patterns including a first conductive pattern in the first region of the substrate and a second conductive pattern in the second region of the substrate, a magnetic tunnel junction on the first conductive pattern, a contact between the magnetic tunnel junction and the first conductive pattern, a through electrode on the second conductive pattern, and a plurality of upper conductive patterns on the magnetic tunnel junction and the through electrode. The contact includes a first contact on the lower conductive patterns, a second contact on the first contact, and a first barrier layer that covers a bottom surface and a lateral surface of the second contact.Type: GrantFiled: April 14, 2020Date of Patent: September 14, 2021Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Kilho Lee, Gwanhyeob Koh
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Publication number: 20210257404Abstract: An embedded device includes a first insulation layer, a second insulation layer on the first insulation layer, a lower electrode contact in the first insulation layer in a first region, a first structure, having a lower electrode, a magnetic tunnel junction, and an upper electrode, in the second insulation layer and contacting the lower electrode contact, a first metal wiring structure through the first and second insulation layers in a second region, a third insulation layer on the second insulation layer, a bit line structure through the third insulation layer and the second insulation layer in the first region, the bit line structure having a first height and contacting the upper electrode, and a second metal wiring structure through the third insulation layer in the second region, the second metal wiring structure contacting the first metal wiring structure, and having a second height lower than the first height.Type: ApplicationFiled: September 22, 2020Publication date: August 19, 2021Inventors: Kilho LEE, Gwanhyeob KOH, Woojin KIM
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Publication number: 20210151502Abstract: A magnetoresistive random access memory device including a first insulating interlayer on a substrate; lower electrode contacts passing through the first insulating interlayer; first structures on the lower electrode contacts, respectively, each of the first structures including a stacked lower electrode, magnetic tunnel junction (MTJ) structure, and upper electrode; a second insulating interlayer on the first structures and the first insulating interlayer, the second insulating interlayer filling a space between the first structures; a third insulating interlayer directly contacting the second insulating interlayer, the third insulating interlayer having a dielectric constant lower than a dielectric constant of the second insulating interlayer; and a bit line passing through the third insulating interlayer and the second insulating interlayer, the bit line contacting the upper electrode of one of the first structures.Type: ApplicationFiled: June 4, 2020Publication date: May 20, 2021Inventors: Woojin KIM, Yongjae KIM, Kilho LEE
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Publication number: 20210134884Abstract: Disclosed is a semiconductor device including first conductive lines, second conductive lines crossing the first conductive lines, and memory cells at intersections between the first conductive lines and the second conductive lines. Each of the memory cells includes a magnetic tunnel junction pattern, a bi-directional switching pattern connected in series to the magnetic tunnel junction pattern, and a conductive pattern between the magnetic tunnel junction pattern and the bi-directional switching pattern.Type: ApplicationFiled: November 3, 2020Publication date: May 6, 2021Applicant: Samsung Electronics Co., Ltd.Inventors: Kilho LEE, Gwanhyeob KOH, Ilmok PARK, Junhee LIM
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Publication number: 20210104575Abstract: A semiconductor device including a substrate that has a first region and a second region, a plurality of lower conductive patterns on the substrate, the plurality of lower conductive patterns including a first conductive pattern in the first region of the substrate and a second conductive pattern in the second region of the substrate, a magnetic tunnel junction on the first conductive pattern, a contact between the magnetic tunnel junction and the first conductive pattern, a through electrode on the second conductive pattern, and a plurality of upper conductive patterns on the magnetic tunnel junction and the through electrode. The contact includes a first contact on the lower conductive patterns, a second contact on the first contact, and a first barrier layer that covers a bottom surface and a lateral surface of the second contact.Type: ApplicationFiled: April 14, 2020Publication date: April 8, 2021Applicant: Samsung Electronics Co., Ltd.Inventors: Kilho LEE, Gwanhyeob KOH
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Publication number: 20210082998Abstract: A magnetic memory device includes a magnetic tunnel junction pattern on a substrate, a first conductive pattern between the substrate and the magnetic tunnel junction pattern, lower contact plugs between the first conductive pattern and the substrate and disposed at respective sides of the magnetic tunnel junction pattern, and second conductive patterns on the lower contact plugs, respectively. The second conductive patterns connect the lower contact plugs to the first conductive pattern. The second conductive patterns include a ferromagnetic material.Type: ApplicationFiled: June 8, 2020Publication date: March 18, 2021Inventors: Kilho Lee, Gwanhyeob Koh
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Patent number: 10897006Abstract: A magnetic memory device including a substrate including a cell region and a peripheral circuit region; a first interlayer insulating layer covering the cell region and the peripheral circuit region of the substrate; interconnection lines in the first interlayer insulating layer; a peripheral conductive line and a peripheral conductive contact on the first interlayer insulating layer on the peripheral circuit region, the peripheral conductive contact being between the peripheral conductive line and a corresponding one of the interconnection lines; a bottom electrode contact on the first interlayer insulating layer on the cell region and connected to a corresponding one of the interconnection lines; and a data storage pattern on the bottom electrode contact, wherein the peripheral conductive line is at a height between a top surface of the bottom electrode contact and a bottom surface of the bottom electrode contact.Type: GrantFiled: February 27, 2019Date of Patent: January 19, 2021Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Kilho Lee, Gwanhyeob Koh, Yongjae Kim, Yoonjong Song
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Patent number: 10861902Abstract: A semiconductor device includes first conductive lines, second conductive lines crossing the first conductive lines, and memory cells at intersections between the first conductive lines and the second conductive lines. Each of the memory cells includes a magnetic tunnel junction pattern, a bi-directional switching pattern connected in series to the magnetic tunnel junction pattern, and a conductive pattern between the magnetic tunnel junction pattern and the bi-directional switching pattern.Type: GrantFiled: June 16, 2018Date of Patent: December 8, 2020Inventors: Kilho Lee, Gwanhyeob Koh, Ilmok Park, Junhee Lim
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Patent number: 10693055Abstract: Magnetic random access memory (MRAM) devices are provided. The MRAM devices may include a magnetic tunnel junction (MTJ) including a free layer and a pinned layer sequentially stacked in a vertical direction and a conductive layer adjacent to the free layer of the MTJ. The conductive layer may include a horizontal portion and first and second protruding portions that protrude away from the horizontal portion and are spaced apart from each other in a horizontal direction that is perpendicular to the vertical direction. A side of the free layer and a side of the horizontal portion may form a straight side.Type: GrantFiled: November 28, 2018Date of Patent: June 23, 2020Assignee: Samsung Electronics Co., Ltd.Inventors: Kilho Lee, Gwanhyeob Koh, Yoonjong Song