Abstract: A method and apparatus for manufacturing substrate based fan-out wafer level packaging is provided. The method includes providing a substrate, applying a first photoresist pattern, depositing copper or a copper alloy, applying a second photoresist pattern, forming chip attach site pillars by depositing a layer of copper or copper alloy, and attaching a semiconductor device via a flip chip bonding. The attaching includes forming a plurality of interconnect bumps between the semiconductor device and the chip attach site and forming a space between the semiconductor device and the substrate. The method further includes encapsulating the semiconductor device, thinning a second side of the substrate, applying a ball grid array pattern on the second side and etching the second side with copper, applying a solder mask coating, attaching a plurality of ball drops, and singulating a unit.

Abstract: A method and apparatus for manufacturing substrate based fan-out wafer level packaging is provided. The method includes providing a substrate, applying a first photoresist pattern, depositing copper or a copper alloy, applying a second photoresist pattern, forming chip attach site pillars by depositing a layer of copper or copper alloy, and attaching a semiconductor device via a flip chip bonding. The attaching includes forming a plurality of interconnect bumps between the semiconductor device and the chip attach site and forming a space between the semiconductor device and the substrate. The method further includes encapsulating the semiconductor device, thinning a second side of the substrate, applying a ball grid array pattern on the second side and etching the second side with copper, applying a solder mask coating, attaching a plurality of ball drops, and singulating a unit.

Abstract: A method and apparatus for manufacturing substrate based fan-out wafer level packaging is provided. The method includes providing a substrate, applying a first photoresist pattern, depositing copper or a copper alloy, applying a second photoresist pattern, forming chip attach site pillars by depositing a layer of copper or copper alloy, and attaching a semiconductor device via a flip chip bonding. The attaching includes forming a plurality of interconnect bumps between the semiconductor device and the chip attach site and forming a space between the semiconductor device and the substrate. The method further includes encapsulating the semiconductor device, thinning a second side of the substrate, applying a ball grid array pattern on the second side and etching the second side with copper, applying a solder mask coating, attaching a plurality of ball drops, and singulating a unit.

Abstract: A method and apparatus for manufacturing substrate based fan-out wafer level packaging is provided. The method includes providing a substrate, applying a first photoresist pattern, depositing copper or a copper alloy, applying a second photoresist pattern, forming chip attach site pillars by depositing a layer of copper or copper alloy, and attaching a semiconductor device via a flip chip bonding. The attaching includes forming a plurality of interconnect bumps between the semiconductor device and the chip attach site and forming a space between the semiconductor device and the substrate. The method further includes encapsulating the semiconductor device, grinding a second side of the substrate, applying a ball grid array pattern on the second side and etching the second side with copper, applying a solder mask coating, attaching a plurality of ball drops, and singulating a unit.

Abstract: An image sensor device is made using an ultra-thin substrate so that the overall device height is less than 1.0 mm. The image sensor includes a flexible circuit substrate having first and second opposing sides, the first side having a central area and an outer, bonding pad area including bonding pads. A sensor integrated circuit (IC) is attached to the central area of the first side of the circuit substrate. The IC has an active area and a peripheral bonding pad area including bonding pads. Wires are wirebonded to respective ones of the IC bonding pads and corresponding ones of the circuit substrate bonding pads to electrically connect the IC and the circuit substrate. A wall having a first end with a step and a second end has its second end attached to an outer portion beyond the outer bonding pad area of the first side of the flexible circuit substrate. The wall at least partially surrounds the sensor integrated circuit.

Abstract: An image sensor device is made using an ultra-thin substrate so that the overall device height is less than 1.0 mm. The image sensor includes a flexible circuit substrate having first and second opposing sides, the first side having a central area and an outer, bonding pad area including bonding pads. A sensor integrated circuit (IC) is attached to the central area of the first side of the circuit substrate. The IC has an active area and a peripheral bonding pad area including bonding pads. Wires are wirebonded to respective ones of the IC bonding pads and corresponding ones of the circuit substrate bonding pads to electrically connect the IC and the circuit substrate. A wall having a first end with a step and a second end has its second end attached to an outer portion beyond the outer bonding pad area of the first side of the flexible circuit substrate. The wall at least partially surrounds the sensor integrated circuit.

Abstract: A stacked multichip package (100) has a base carrier (102) having a top side (108) and a bottom side (110), a bottom integrated circuit die (104) having a bottom surface attached to the base carrier top side (108), and a top integrated circuit die (106 attached to a top surface of the bottom die (104). The top die (106) is attached to the bottom die (104) with a die attach material (118) having particles (120) blended therein is dispensed onto the top surface of the bottom die. The particles (120) blended into the die attach material (118) maintain a predetermined spacing between the bottom die and the top die so that wirebonds connecting the bottom die (104) to the base carrier (102) are not damaged when the top die (106) is attached to the bottom die (104).