Patents by Inventor Kim Pin Tan
Kim Pin Tan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11941336Abstract: Circuit devices include a first chip that includes functional blocks. A second chip has routing circuitry that provides configurable signal communications between functional blocks of the first chip and configuration memory that controls the routing circuitry and that further controls operation of the functional blocks of the first chip.Type: GrantFiled: November 10, 2021Date of Patent: March 26, 2024Assignee: OPPSTAR TECHNOLOGY SDN BHDInventors: Kim Pin Tan, Hun Wah Cheah
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Publication number: 20230288953Abstract: Circuit devices, configurable circuit devices, and methods of configuring the same include a first logic block and a routing block. The routing block routes a clock signal to the first logic block and includes a selectable delay circuit with delay paths and a multiplexer that selects one of the delay paths. Each of the delay paths delays the clock signal by a different amount.Type: ApplicationFiled: March 9, 2022Publication date: September 14, 2023Inventors: Kim Pin Tan, Hun Wah Cheah
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Publication number: 20230140876Abstract: Circuit devices include a first chip that includes functional blocks. A second chip has routing circuitry that provides configurable signal communications between functional blocks of the first chip and configuration memory that controls the routing circuitry and that further controls operation of the functional blocks of the first chip.Type: ApplicationFiled: November 10, 2021Publication date: May 11, 2023Inventors: Kim Pin Tan, Hun Wah Cheah
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Publication number: 20230077881Abstract: Configurable circuits include an input selection region, a computation region, a switching region, and an output region. The input selection region includes a set of input multiplexers and selects and routes input signals. The computation region includes a set of lookup tables, each lookup table being coupled to selected signals from the input selection stage to generate a respective output signal. The switching region includes a set of output multiplexers, each output multiplexer being coupled to output signals from the set of lookup tables to provide circuit outputs responsive to respective output selection signals. The output region includes a domino logic stage, having a set of transistors, coupled to output signals from the set of lookup tables to provide circuit outputs that determine combinations of the signals output by the set of lookup tables.Type: ApplicationFiled: September 14, 2021Publication date: March 16, 2023Inventors: Kim Pin Tan, Kok Keong Liaw, Hun Wah Cheah
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Patent number: 8863061Abstract: Providing ASIC equivalents of FPGAs is facilitated and made more efficient and economical by using an ASIC architecture including a plurality of so-called hybrid logic elements (“HLEs”), each of which can provide a portion of the full functionality of an FPGA logic element (“LE”). The functionality of each FPGA LE implementing a user's logic design can be mapped to one or more HLEs without re-synthesis of the user's logic. Only as many HLEs as are necessary are used to perform the functions of each LE. The one-for-one equivalence between each LE and either (1) one HLE or (2) a group of HLEs facilitates mapping (without re-synthesis) in either direction between FPGA and ASIC designs.Type: GrantFiled: July 31, 2013Date of Patent: October 14, 2014Assignee: Altera CorporationInventors: Kar Keng Chua, Sammy Cheung, Hee Kong Phoon, Kim Pin Tan, Wei Lian Goay
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Patent number: 8659334Abstract: Circuits and a method for tuning an integrated circuit (IC) are disclosed. The IC includes multiple programmable fuses coupled to a control block. The programmable fuses used may be one-time programmable (OTP) fuses. The control block reads settings or data stored in the programmable fuses. A tuning circuit coupled to the control block receives the delay transmitted by the control block. The tuning circuit allows tuning of the IC without changes to the fabrication mask. The tuning circuit may include delay chains to provide additional delay to the IC when needed and the delay in the tuning circuit is configured based on the delay value stored in the programmable fuses and transmitted by the control block.Type: GrantFiled: July 6, 2012Date of Patent: February 25, 2014Assignee: Altera CorporationInventors: Teik Wah Lim, Eng Huat Lee, Ie Chen Chia, Thow Pang Chong, Boon Jin Ang, Kim Pin Tan
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Publication number: 20130314122Abstract: Providing ASIC equivalents of FPGAs is facilitated and made more efficient and economical by using an ASIC architecture including a plurality of so-called hybrid logic elements (“HLEs”), each of which can provide a portion of the full functionality of an FPGA logic element (“LE”). The functionality of each FPGA LE implementing a user's logic design can be mapped to one or more HLEs without re-synthesis of the user's logic. Only as many HLEs as are necessary are used to perform the functions of each LE. The one-for-one equivalence between each LE and either (1) one HLE or (2) a group of HLEs facilitates mapping (without re-synthesis) in either direction between FPGA and ASIC designs.Type: ApplicationFiled: July 31, 2013Publication date: November 28, 2013Applicant: Altera CorporationInventors: Kar Keng Chua, Sammy Cheung, Hee Kong Phoon, Kim Pin Tan, Wei Lian Goay
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Patent number: 8504963Abstract: Providing ASIC equivalents of FPGAs is facilitated and made more efficient and economical by using an ASIC architecture including a plurality of so-called hybrid logic elements (“HLEs”), each of which can provide a portion of the full functionality of an FPGA logic element (“LE”). The functionality of each FPGA LE implementing a user's logic design can be mapped to one or more HLEs without re-synthesis of the user's logic. Only as many HLEs as are necessary are used to perform the functions of each LE. The one-for-one equivalence between each LE and either (1) one HLE or (2) a group of HLEs facilitates mapping (without re-synthesis) in either direction between FPGA and ASIC designs.Type: GrantFiled: September 13, 2012Date of Patent: August 6, 2013Assignee: Altera CorporationInventors: Kar Keng Chua, Sammy Cheung, Hee Kong Phoon, Kim Pin Tan, Wei Lian Goay
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Publication number: 20130002295Abstract: Providing ASIC equivalents of FPGAs is facilitated and made more efficient and economical by using an ASIC architecture including a plurality of so-called hybrid logic elements (“HLEs”), each of which can provide a portion of the full functionality of an FPGA logic element (“LE”). The functionality of each FPGA LE implementing a user's logic design can be mapped to one or more HLEs without re-synthesis of the user's logic. Only as many HLEs as are necessary are used to perform the functions of each LE. The one-for-one equivalence between each LE and either (1) one HLE or (2) a group of HLEs facilitates mapping (without re-synthesis) in either direction between FPGA and ASIC designs.Type: ApplicationFiled: September 13, 2012Publication date: January 3, 2013Applicant: ALTERA CORPORATIONInventors: Kar Keng Chua, Sammy Cheung, Hee Kong Phoon, Kim Pin Tan, Wei Lian Goay
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Publication number: 20120274375Abstract: Circuits and a method for tuning an integrated circuit (IC) are disclosed. The IC includes multiple programmable fuses coupled to a control block. The programmable fuses used may be one-time programmable (OTP) fuses. The control block reads settings or data stored in the programmable fuses. A tuning circuit coupled to the control block receives the delay transmitted by the control block. The tuning circuit allows tuning of the IC without changes to the fabrication mask. The tuning circuit may include delay chains to provide additional delay to the IC when needed and the delay in the tuning circuit is configured based on the delay value stored in the programmable fuses and transmitted by the control block.Type: ApplicationFiled: July 6, 2012Publication date: November 1, 2012Inventors: Teik Wah Lim, Eng Huat Lee, Ie Chen Chia, Thow Pang Chong, Boon Jin Ang, Kim Pin Tan
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Patent number: 8291355Abstract: Providing ASIC equivalents of FPGAs is facilitated and made more efficient and economical by using an ASIC architecture including a plurality of so-called hybrid logic elements (“HLEs”), each of which can provide a portion of the full functionality of an FPGA logic element (“LE”). The functionality of each FPGA LE implementing a user's logic design can be mapped to one or more HLEs without re-synthesis of the user's logic. Only as many HLEs as are necessary are used to perform the functions of each LE. The one-for-one equivalence between each LE and either (1) one HLE or (2) a group of HLEs facilitates mapping (without re-synthesis) in either direction between FPGA and ASIC designs.Type: GrantFiled: December 14, 2010Date of Patent: October 16, 2012Assignee: Altera CorporationInventors: Kar Keng Chua, Sammy Cheung, Hee Kong Phoon, Kim Pin Tan, Wei Lian Goay
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Patent number: 8232823Abstract: Circuits and a method for tuning an integrated circuit (IC) are disclosed. The IC includes multiple programmable fuses coupled to a control block. The programmable fuses used may be one-time programmable (OTP) fuses. The control block reads settings or data stored in the programmable fuses. A tuning circuit coupled to the control block receives the delay transmitted by the control block. The tuning circuit allows tuning of the IC without changes to the fabrication mask. The tuning circuit may include delay chains to provide additional delay to the IC when needed and the delay in the tuning circuit is configured based on the delay value stored in the programmable fuses and transmitted by the control block.Type: GrantFiled: June 5, 2009Date of Patent: July 31, 2012Assignee: Altera CorporationInventors: Teik Wah Lim, Eng Huat Lee, Ie Chen Chia, Thow Pang Chong, Boon Jin Ang, Kim Pin Tan
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Publication number: 20110084727Abstract: Providing ASIC equivalents of FPGAs is facilitated and made more efficient and economical by using an ASIC architecture including a plurality of so-called hybrid logic elements (“HLEs”), each of which can provide a portion of the full functionality of an FPGA logic element (“LE”). The functionality of each FPGA LE implementing a user's logic design can be mapped to one or more HLEs without re-synthesis of the user's logic. Only as many HLEs as are necessary are used to perform the functions of each LE. The one-for-one equivalence between each LE and either (1) one HLE or (2) a group of HLEs facilitates mapping (without re-synthesis) in either direction between FPGA and ASIC designs.Type: ApplicationFiled: December 14, 2010Publication date: April 14, 2011Inventors: Kar Keng Chua, Sammy Cheung, Hee Kong Phoon, Kim Pin Tan, Wei Lian Goay
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Patent number: 7870513Abstract: Providing ASIC equivalents of FPGAs is facilitated and made more efficient and economical by using an ASIC architecture including a plurality of so-called hybrid logic elements (“HLEs”), each of which can provide a portion of the full functionality of an FPGA logic element (“LE”). The functionality of each FPGA LE implementing a user's logic design can be mapped to one or more HLEs without re-synthesis of the user's logic. Only as many HLEs as are necessary are used to perform the functions of each LE. The one-for-one equivalence between each LE and either (1) one HLE or (2) a group of HLEs facilitates mapping (without re-synthesis) in either direction between FPGA and ASIC designs.Type: GrantFiled: May 7, 2007Date of Patent: January 11, 2011Assignee: Altera CorporationInventors: Kar Keng Chua, Sammy Cheung, Hee Kong Phoon, Kim Pin Tan, Wei Lian Goay
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Patent number: 7243315Abstract: As part of a process for producing a structured ASIC that is functionally equivalent to an FPGA that has been programmed to perform a user's logic design, a compilation of that design that has been prepared for ASIC implementation is converted to a physical layout of the structured ASIC. The production of this physical layout honors timing constraints supplied by the user, and also preserves functional equivalence to the reference programmed FPGA. The structured ASIC can be manufactured from the physical layout produced.Type: GrantFiled: May 31, 2005Date of Patent: July 10, 2007Assignee: Altera CorporationInventors: Kim Pin Tan, Kar Keng Chua
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Patent number: 6988258Abstract: A mask-programmable logic device includes logical building blocks that can be connected together to form various logical units for programmable logic. Functionality of a comparable conventional programmable logic device can be provided with fewer gates in this way than by providing all of the gates normally present on that comparable conventional programmable logic device, resulting in fewer unused gates in the devices once mask-programmed.Type: GrantFiled: December 9, 2002Date of Patent: January 17, 2006Assignee: Altera CorporationInventors: Kim Pin Tan, Boon Jin Ang, Bee Yee Ng
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Publication number: 20040111691Abstract: A mask-programmable logic device includes logical building blocks that can be connected together to form various logical units for programmable logic. Functionality of a comparable conventional programmable logic device can be provided with fewer gates in this way than by providing all of the gates normally present on that comparable conventional programmable logic device, resulting in fewer unused gates in the devices once mask-programmed.Type: ApplicationFiled: December 9, 2002Publication date: June 10, 2004Inventors: Kim Pin Tan, Boon Jin Ang, Bee Yee Ng