Patents by Inventor Kim R. Stevens

Kim R. Stevens has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Power grid layout techniques on integrated circuits
    Patent number: 7462941
    Abstract: Techniques are provided for reducing the power supply voltage drop introduced by routing conductive traces on an integrated circuit. Techniques for reducing variations in the power supply voltages received in different regions of an integrated circuit are also provided. Power supply voltages are routed within an integrated circuit across conductive traces. The conductive traces are coupled to solder bumps that receive power supply voltages from an external source. Alternate ones of the traces receive a high power supply voltage VDD and a low power supply voltage VSS. The conductive traces reduce the voltage drop in the power supply voltages by providing shorter paths to route the power supply voltages to circuit elements on the integrated circuit.
    Type: Grant
    Filed: September 27, 2005
    Date of Patent: December 9, 2008
    Assignee: Telairity Semiconductor, Inc.
    Inventors: John Campbell, Kim R. Stevens, Luigi DiGregorio
  • Power grid layout techniques on integrated circuits
    Patent number: 6998719
    Abstract: Techniques are provided for reducing power supply voltage drop introduced by routing conductive traces on an integrated circuit. Techniques for reducing variations in the power supply voltages received in different regions of an integrated circuit are also provided. Power supply voltages are routed within an integrated circuit across conductive traces. The conductive traces are coupled to bond pads that receive power supply voltages from an external source. Alternate ones of the traces receive a high power supply voltage VDD and a low power supply voltage VSS. The conductive traces reduce the voltage drop in the power supply voltages by providing shorter paths to route the power supply voltages to circuit elements on the integrated circuit.
    Type: Grant
    Filed: July 30, 2003
    Date of Patent: February 14, 2006
    Assignee: Telairity Semiconductor, Inc.
    Inventors: John Campbell, Kim R. Stevens, Luigi DiGregorio