Abstract: A data processing apparatus is provided comprising: a plurality of input lanes and a plurality of corresponding output lanes. Processing circuitry executes a first vector instruction and a second vector instruction. The first vector instruction specifies a target of output data from the corresponding output lanes that is specified as a source of input data to the input lanes by the second vector instruction. Mask circuitry stores a first mask that defines a first set of the output lanes that are valid for the first vector instruction, and stores a second mask that defines a second set of the output lanes that are valid for the second vector instruction. The first set and the second set are mutually exclusive. Issue circuitry begins processing of the second vector instruction at a lane index prior to completion of the first vector instruction at the lane index.

Abstract: An apparatus and a method are described, the apparatus comprising: processing circuitry adapted to execute instructions from an instruction stream comprising a state transition instruction followed by a further instruction, wherein the processing circuitry is responsive to the state transition instruction to change a security state of the processing circuitry; issue circuitry adapted to issue the further instruction to be speculatively executed prior to the state transition instruction being completed, the further instruction having a requirement in respect of the security state; and completion circuitry adapted to perform a completion operation on the further instruction comprising checking whether the requirement in respect of the security state is met.

Abstract: In a data processing apparatus loop end prediction is carried out to predict whether a branch represented by a loop end instruction will be taken, branching to the start of the loop for a further iteration to be carried out, or will be not taken leading to the further instructions following the loop. A loop iteration counter at the fetch stage of the apparatus maintains a count on the basis of which the prediction is made. The loop iteration counter is decremented both by loop end instructions reaching the end of the pipeline for which no prediction was made and by later loop end instructions for which a prediction is made, once it has been established that a loop is being executed. This dual counting mechanism allows “shadow” loop end instructions, which were already in the pipeline by the time it was established that a loop is being executed, to be accounted for.

Abstract: An apparatus comprises a set-associative cache comprising a plurality of sets of cache entries, and cache replacement policy storage circuitry to store a plurality of local replacement policy entries. Each local replacement policy entry comprises local replacement policy information specific to a corresponding set of the set-associative cache. Cache control circuitry controls replacement of cache entries of the set-associative cache based on the local replacement policy information stored in the cache replacement policy storage circuitry. The cache replacement policy storage circuitry stores local replacement policy entries for a proper subset of sets of the set-associative cache.

Abstract: A data processing apparatus is provided comprising: a plurality of input lanes and a plurality of corresponding output lanes. Processing circuitry executes a first vector instruction and a second vector instruction. The first vector instruction specifies a target of output data from the corresponding output lanes that is specified as a source of input data to the input lanes by the second vector instruction. Mask circuitry stores a first mask that defines a first set of the output lanes that are valid for the first vector instruction, and stores a second mask that defines a second set of the output lanes that are valid for the second vector instruction. The first set and the second set are mutually exclusive. Issue circuitry begins processing of the second vector instruction at a lane index prior to completion of the first vector instruction at the lane index.

Abstract: A system, apparatus and method for enabling a FIFO-like (first-in-first-out) communication between a plurality of executing processes that are distributed throughout a computing system. Embodiments exploit locality in the hierarchy of the cache memory and communication busses within the computing system to enable the passing of messages or streams of bytes with a low latency and high throughput. In addition, this allows for participating components to be very simple, or very sophisticated, but still benefit from the improved communications patterns.

Abstract: An apparatus comprises processing circuitry to process data access operations specifying a virtual address of data to be loaded from or stored to a data store, and proxy identifier determining circuitry to determine a proxy identifier for a data access operation to be processed by the data access circuitry, the proxy identifier having fewer bits than a physical address corresponding to the virtual address specified by the data access operation. The processing circuitry comprises at least one buffer to buffer information (including the proxy identifier) associated with one or more pending data access operations awaiting processing. Address translation circuitry determines the physical address corresponding to the virtual address specified for a data access operation after that data access operation has progressed beyond said at least one buffer.

Abstract: An apparatus comprises a set-associative cache comprising a plurality of sets of cache entries, and cache replacement policy storage circuitry to store a plurality of local replacement policy entries. Each local replacement policy entry comprises local replacement policy information specific to a corresponding set of the set-associative cache. Cache control circuitry controls replacement of cache entries of the set-associative cache based on the local replacement policy information stored in the cache replacement policy storage circuitry. The cache replacement policy storage circuitry stores local replacement policy entries for a proper subset of sets of the set-associative cache.

Abstract: A system, apparatus and method for enabling a FIFO-like (first-in-first-out) communication between a plurality of executing processes that are distributed throughout a computing system. Embodiments exploit locality in the hierarchy of the cache memory and communication busses within the computing system to enable the passing of messages or streams of bytes with a low latency and high throughput. In addition, this allows for participating components to be very simple, or very sophisticated, but still benefit from the improved communications patterns.

Abstract: An apparatus and method are provided for handling access requests. The apparatus has processing circuitry for processing a plurality of program threads to perform data processing operations on data, where the operations identify the data using virtual addresses, and the virtual addresses are mapped to physical addresses within a memory system. The cache storage has a plurality of cache entries to store data, an aliasing condition existing when multiple virtual addresses map to the same physical address, and allocation of data into the cache storage being constrained to prevent multiple cache entries of the cache storage simultaneously storing data for the same physical address.

Abstract: An apparatus and method are provided for determining a recovery point from which to resume instruction execution following handling of an unexpected change in instruction flow. The apparatus comprises processing circuitry having an associated instruction set architecture, and arranged to execute software comprising instructions defined by the instruction set architecture, and control circuitry for controlling operation of the processing circuitry according to constraints defined by the instruction set architecture. The instruction set architecture defines a default recovery point constraint for determining a recovery point from which to resume instruction execution following handling of an unexpected change in instruction flow.

Abstract: An apparatus and method are provided for handling access requests. The apparatus has processing circuitry for processing a plurality of program threads to perform data processing operations on data, where the operations identify the data using virtual addresses, and the virtual addresses are mapped to physical addresses within a memory system. The cache storage has a plurality of cache entries to store data, an aliasing condition existing when multiple virtual addresses map to the same physical address, and allocation of data into the cache storage being constrained to prevent multiple cache entries of the cache storage simultaneously storing data for the same physical address.

Abstract: An apparatus and method are provided for determining a recovery point from which to resume instruction execution following handling of an unexpected change in instruction flow. The apparatus comprises processing circuitry having an associated instruction set architecture, and arranged to execute software comprising instructions defined by the instruction set architecture, and control circuitry for controlling operation of the processing circuitry according to constraints defined by the instruction set architecture. The instruction set architecture defines a default recovery point constraint for determining a recovery point from which to resume instruction execution following handling of an unexpected change in instruction flow.

Abstract: An apparatus comprises processing circuitry to process data access operations specifying a virtual address of data to be loaded from or stored to a data store, and proxy identifier determining circuitry to determine a proxy identifier for a data access operation to be processed by the data access circuitry, the proxy identifier having fewer bits than a physical address corresponding to the virtual address specified by the data access operation. The processing circuitry comprises at least one buffer to buffer information (including the proxy identifier) associated with one or more pending data access operations awaiting processing. Address translation circuitry determines the physical address corresponding to the virtual address specified for a data access operation after that data access operation has progressed beyond said at least one buffer.