Abstract: Systems and techniques relating to hardware alias detection and management in caches are described. A cache controller can receive a cache request that specifies a virtual address, which includes a virtual page number (VPN) and a page offset; access, concurrently, one or more primary tags in a slot of the cache corresponding to a primary cache index that is based on a portion of the page offset and a portion of the VPN and one or more secondary tags in one or more slots corresponding to one or more secondary cache indices that are based on the portion of the page offset and one or more variations of the portion of the VPN; and determine whether there are any primary or secondary matching ways. The controller can write store data to a primary matching way if it exists and perform an alias management operation if any secondary matching ways exist.

Abstract: A circuit includes a Virtually Indexed Physically Tagged (VIPT) cache and a cache coherency circuit. The VIPT cache includes a plurality of sets and performs a memory operation by selecting, using a Virtual Set Address (VSA), a first tag of a first set. The cache coherency circuit is to detect cache aliasing during memory operations of the VIPT cache when a second tag maps a physical address to a second set of the VIPT cache, the second set being different than the first set. A method of managing a VIPT cache includes performing, by the VIPT cache, a memory operation and determining, using a cache coherency protocol, that cache aliasing has occurred during the memory operation.

Abstract: Systems, methods, and other embodiments associated with providing limited writing in a memory hierarchy are described. According to one embodiment, an apparatus includes a plurality of memory devices sequentially configured in a memory hierarchy. The apparatus also includes a first logic configured to execute a first command to initiate a sequence of write operations to write data to the plurality of memory devices in the memory hierarchy via propagation of the data sequentially through the memory hierarchy. The apparatus further includes a second logic configured to execute a second command to initiate an interruption of the sequence of write operations by indicating to at least one memory device of the plurality of memory devices to terminate the propagation of the data through the memory hierarchy prior to completing the propagation.

Abstract: Systems, methods, and other embodiments are described that are associated with selective shorting of clock branches. In one embodiment, an apparatus includes a selective shorting device connected between a first clock branch that conducts a slow clock signal having a first frequency and a second clock branch that conducts a fast clock signal having a second frequency that is an integer multiple of the first frequency. The selective shorting device is configured to electrically connect and disconnect the first clock branch and the second clock branch. The selective shorting control mechanism is configured to control the selective shorting device to electrically connect the clock branches during a controlling portion of the slow clock signal.

Abstract: A processor including architectural registers used to execute instructions and a renaming module to rename the architectural registers to physical registers in response to receiving instructions. A first table stores pointers to the physical registers storing data generated in response to the processor completing execution of instructions. A second table stores pointers to the physical registers storing data to be generated by instructions received but not executed by the processor and used by instructions to be received by the processor. An execution module executes instructions and discards one or more instructions received but not executed by the processor in response to an event. An updating module updates pointers in the second table in response to the event. The updated pointers are generated based on pointers stored in the first table at a time of occurrence of the event and instructions not discarded by the execution module.

Abstract: An integrated circuit including a cache and first and second modules. The cache is folded a predetermined number of times. The cache includes arrays and storage elements. Each of the arrays includes respective ones of the storage elements. The arrays store a cache line. The cache line includes segments of data. The segments of data are stored in two or more of the arrays. Each of the segments of data is stored in a corresponding one of the storage elements. The first module receives a first identifier of one of the segments of data and a second identifier of a set of the storage elements. The first module determines an index based on the first and second identifiers. The second module, based on the index, accesses one of the segments of data from the two or more of the arrays and outputs the one of the segments of data.

Abstract: Systems, methods, and other embodiments associated with controlling a clocking rate of a processor clock are described. According to one embodiment, an apparatus includes a register, a selector, and a clock gate. The register stores a set of bits arranged in a clocking pattern. In response to receiving an edge of a first clock signal, the selector selects a bit of the set of bits in the register. With each edge of the first clock signal, the selector selects a next bit in the clocking pattern. The clock gate implements a conjunction of the selected bit and the edge. The clock gate then outputs the conjunction of the selected bit and the edge as a second clock signal.

Abstract: A method for detecting patterns of memory accesses in a computing system with out-of-order program execution is provided. The method comprises identifying a first memory operation instruction that is part of a memory stream that would benefit from memory prefetches, marking with program order a plurality of other memory operation instructions prior to execution that are part of the same memory stream as the first memory operation instruction while the plurality of other memory operation instructions are in program order, and, subsequent to out of program order execution of at least two of the plurality of marked memory operation instructions but before execution of all of the plurality of marked memory operation instructions, determining an expected offset value between memory addresses to be accessed by consecutively marked memory operation instructions using the marked memory operation instructions that have executed.

Abstract: Systems and methods for writing data to a data storage structure are provided. A data storage structure includes an array of storage locations. A plurality of write ports are configured to write a number of elements to the array simultaneously. The array of storage locations is arranged logically into N groups. Each group of the N groups is associated with a single multiplexer of a plurality of multiplexers. The single multiplexer is configured to receive inputs from the plurality of write ports and to select a single input to be written to a storage location of the associated group.

Abstract: Some of the embodiments of the present disclosure provide a system comprising a queue configured to store a plurality of instructions, wherein the queue comprises a plurality of entries, wherein each entry of the plurality of entries of the queue is associated with a corresponding identification comprising a corresponding wrap bit and corresponding position bits; and a processing unit configured to receive (i) a first identification associated with a first entry storing a first instruction, and (ii) a second identification associated with a second entry storing a second instruction, compare (i) a first wrap bit of the first identification and (ii) a second wrap bit of the second identification, and determine a relative age of the first instruction with respect to the second instruction.

Abstract: A method for expanding preload capabilities of a memory to encompass a register file is provided. The method comprises predicting an address of a memory location containing data to be accessed by a first memory operation instruction that has not yet executed, prior to the first memory operation instruction executing moving the data in the memory location to an unassigned register file entry, and causing a renaming register to assign the register file entry to an architectural register. Responsive to the renaming register assigning the register file entry to the architectural register, the method further comprises permitting a second instruction to execute using the data moved to the register file, wherein the second instruction is dependent on the first memory operation instruction.

Abstract: Systems and methods for writing data from a caching agent to a main memory in a computer system are provided. In systems and methods for writing data from a caching agent to a main memory in a computer system, a notice of an occurrence of a triggering event is received. In response to the receipt of the notice, data is retrieved from a storage array of the caching agent in accordance with a pre-clean criterion. The pre-clean criterion identifies the data that is being retrieved from the storage array prior to receiving a command on the data. The data is written to the main memory, where the writing of the data causes a memory address associated with the data to have identical contents in the storage array and in the main memory.

Abstract: Systems, methods, and other embodiments associated with reducing interrupt latency are described. According to one embodiment, an apparatus includes a buffer storing instructions awaiting execution by an execution device. The apparatus also includes an interrupt logic that, in response to receiving an interrupt, classifies instructions as either safe or unsafe. An unsafe instruction will cause the instructions to execute in a manner inconsistent with an instruction set architecture. The interrupt logic also establishes an interrupt boundary between safe and unsafe instructions, and causes the interrupt to be processed at the interrupt boundary such that the interrupt is processed before processing of the unsafe instructions.

Abstract: A system and method of tracking multiple non-identification tagged requests in a system with multiple responders are disclosed. In one embodiment, an electronic memory system comprises a memory configured to implement a plurality of response queues, wherein one response queue is associated with one responder from a plurality of responders, and wherein a responder is a device capable of resolving the memory request. A tracking module is configured to assign identification information to a memory request that is received and store the identification information in one or more queues of the plurality of response queues; and to transmit the memory request to each responder that is associated with the one or more queues. A response module is configured to associate the identification information in the one or more queues with a response upon receiving the response from the one or more responders.

Abstract: A system and method of tracking multiple non-identification tagged requests in a system with multiple responders using one or more tracking queues. In some embodiments, the system and method may be implemented in a snoop filter covering multiple caches. In some embodiments, a data-less bus query may be used to update the status of a requested line.

Abstract: Systems, methods, and other embodiments associated with selective shorting are described. According to one embodiment, an apparatus includes a selective shorting device connected between clock branches. The selective shorting device is configured to selectively electrically connect the clock branches to one another and to selectively electrically disconnect the clock branches from one another. The apparatus also includes a selective shorting control mechanism that controls the selective shorting device to electrically connect the clock branches during a controlling portion of a clock signal. The selective shorting control mechanism is configured to electrically disconnect the clock branches in the absence of the controlling portion.

Abstract: A system and method of tracking multiple non-identification tagged requests in a system with multiple responders using one or more tracking queues. In some embodiments, the system and method may be implemented in a snoop filter covering multiple caches. In some embodiments, a data-less bus query may be used to update the status of a requested line.

Abstract: Systems, methods, and other embodiments associated with selective shorting are described. According to one embodiment, an apparatus includes a selective shorting device connected between clock branches. The selective shorting device is configured to selectively electrically connect the clock branches to one another and to selectively electrically disconnect the clock branches from one another. The apparatus also includes a selective shorting control mechanism that controls the selective shorting device to electrically connect the clock branches during a controlling portion of a clock signal. The selective shorting control mechanism is configured to electrically disconnect the clock branches in the absence of the controlling portion.