Abstract: A method of manufacturing a stamper/imprinter for patterning of a recording medium via thermally assisted nano-imprint lithography, comprising steps of: providing a first stamper/imprinter comprising a topographically patterned surface having a correspondence to a selected pattern to be formed in a surface of the medium; injection molding a layer of a polymeric material in conformal contact with the topographically patterned surface of the first stamper/imprinter; and separating the layer of polymeric material from the topographically patterned surface of the first stamper/imprinter to form a second stamper/imprinter comprising a topographically patterned stamping/imprinting surface including a plurality of projections and depressions with dimensions and spacings having a correspondence to the selected pattern to be formed in a surface of the medium.

Abstract: In one illustrative example, a method of making a read sensor of a magnetic head involves forming a barrier structure which surrounds a central mask formed over a plurality of read sensor layers; etching the read sensor layers to form the read sensor below the mask; and depositing, with use of the mask and the barrier structure, hard bias and lead layers to form around the read sensor. The barrier structure may be formed by, for example, depositing one or more barrier structure layers over the read sensor layers and performing a photolithography process. The barrier structure physically blocks materials being deposited at relatively low angles (e.g. angles at or below 71 degrees) so as to reduce their formation far underneath the mask (e.g. when using a bridged mask), which could otherwise form an electrical short, and/or to improve the symmetry of the deposited materials around the read sensor.

Abstract: In one illustrative example, a method of making a read sensor of a magnetic head involves forming a barrier structure which surrounds a central mask formed over a plurality of read sensor layers; etching the read sensor layers to form the read sensor below the mask; and depositing, with use of the mask and the barrier structure, hard bias and lead layers to form around the read sensor. The barrier structure may be formed by, for example, depositing one or more barrier structure layers over the read sensor layers and performing a photolithography process. The barrier structure physically blocks materials being deposited at relatively low angles (e.g. angles at or below 71 degrees) so as to reduce their formation far underneath the mask (e.g. when using a bridged mask), which could otherwise form an electrical short, and/or to improve the symmetry of the deposited materials around the read sensor.

Abstract: An electrical conductor for use in an electronic structure is disclosed which includes a conductor body that is formed of an alloy including between about 0.001 atomic % and about 2 atomic % of an element selected from the group consisting of Ti, Zr, In, Sn and Hf; and a liner abutting the conductor body which is formed of an alloy that includes Ta, W, Ti, Nb and V. The invention further discloses a liner for use in a semiconductor interconnect that is formed of a material selected from the group consisting of Ti, Hf, In, Sn, Zr and alloys thereof, TiCu3, Ta1−XTix, Ta1−X, Hfx, Ta1−X, Inxy, Ta1−XSnx, Ta1−XZrx.

Abstract: An electrical conductor for use in an electronic structure is disclosed which includes a conductor body that is formed of an alloy including between about 0.001 atomic % and about 2 atomic % of an element selected from the group consisting of Ti, Zr, In, Sn and Hf; and a liner abutting the conductor body which is formed of an alloy that includes Ta, W, Ti, Nb and V. The invention further discloses a liner for use in a semiconductor interconnect that is formed of a material selected from the group consisting of Ti, Hf, In, Sn, Zr and alloys thereof, TiCu3, Ta1−XTix, Ta1−XHfx, Ta1−XInxy, Ta1−XSnx, Ta1−XZrx.

Abstract: A method for forming buried oxide regions below a single crystal semiconductor layer incorporating the steps of forming epitaxial layers having different rates of oxidation with the lower layer having a faster rate of oxidation and oxidizing the layers through an opening in a mask. A plurality of oxide isolated FET's may be formed. The invention reduces the problem of source/drain parasitic capacitance and short channel effects while isolating FET's and eliminating floating body effects of an FET by selectively oxidizing semiconductor layers.

Abstract: A method for forming buried oxide regions below a single crystal semiconductor layer incorporating the steps of forming epitaxial layers having different rates of oxidation with the lower layer having a faster rate of oxidation and oxidizing the layers through an opening in a mask. A plurality of oxide isolated FET's may be formed. The invention reduces the problem of source/drain parasitic capacitance and short channel effects while isolating FET's and eliminating floating body effects of an FET by selectively oxidizing semiconductor layers.

Abstract: Fine epitaxial patterns of yttrium barium copper oxide on a strontium titanate substrate are provided by using a silicon nitride mask to define the pattern to be formed. A thin film of yttrium barium copper oxide is placed on the silicon nitride mask and exposed portions of strontium titanate substrate. Where the yttrium barium copper oxide is in contact with the silicon nitride mask, it is nonepitaxial in crystal structure. Where the yttrium barium copper oxide contacts the strontium titanate substrate in the openings, it is epitaxial in structure forming fine patterns that become superconducting below the critical transition temperature. A channel can be formed in the strontium titanate substrate. The epitaxial yttrium barium copper oxide pattern is formed in this channel to minimize possible exposure to the silicon nitride mask.