Patents by Inventor Kim Yong Goh
Kim Yong Goh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10658238Abstract: Embodiments are directed to a package that includes an electric device having a recess. In one embodiment, the electric device is a sensor and the recess reduces signal drift of the sensor caused by thermal expansion of the package. In another embodiment, the recess is substantially filled with adhesive material, thus increasing adhesion between the electric device and a substrate of the package while at the same time allowing for lower adhesive fillets.Type: GrantFiled: October 16, 2017Date of Patent: May 19, 2020Assignee: STMICROELECTRONICS PTE LTDInventors: Kim-Yong Goh, Xueren Zhang, Yiyi Ma
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Publication number: 20180040514Abstract: Embodiments are directed to a package that includes an electric device having a recess. In one embodiment, the electric device is a sensor and the recess reduces signal drift of the sensor caused by thermal expansion of the package. In another embodiment, the recess is substantially filled with adhesive material, thus increasing adhesion between the electric device and a substrate of the package while at the same time allowing for lower adhesive fillets.Type: ApplicationFiled: October 16, 2017Publication date: February 8, 2018Inventors: Kim-Yong Goh, Xueren Zhang, Yiyi Ma
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Patent number: 9824924Abstract: Embodiments are directed to a package that includes an electric device having a recess. In one embodiment, the electric device is a sensor and the recess reduces signal drift of the sensor caused by thermal expansion of the package. In another embodiment, the recess is substantially filled with adhesive material, thus increasing adhesion between the electric device and a substrate of the package while at the same time allowing for lower adhesive fillets.Type: GrantFiled: March 29, 2013Date of Patent: November 21, 2017Assignee: STMicroelectronics Pte Ltd.Inventors: Kim-Yong Goh, Xueren Zhang, Yiyi Ma
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Patent number: 9679870Abstract: An integrated circuit (IC) device includes an IC and encapsulating material surrounding the IC. Leads are coupled to the IC and extend outwardly from sides of the encapsulating material, with each lead having three contiguous exposed segments with upper and lower bends defining a Z-shape. In another example, the leads include an upper horizontal segment, lower horizontal segment, and intermediate curved segment extending upwardly from the upper horizontal segment and downwardly to the lower horizontal segment.Type: GrantFiled: December 10, 2014Date of Patent: June 13, 2017Assignee: STMicroelectronics Pte LtdInventors: Yiyi Ma, Kim-Yong Goh, Xueren Zhang, Wei Zhen Goh
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Patent number: 9620438Abstract: An electronic device includes an integrated circuit chip mounted to a heat slug. The heat slug has a peripheral region having first thickness along a first direction, the peripheral region surrounding a recess region (having a second, smaller, thickness along the first direction) that defines a chip mounting surface along a second direction perpendicular to the first direction. The recess region defines side borders and a nook extends into the heat slug along the side borders. An insulating body embeds the integrated circuit one chip and heat slug. Material of the insulating body fills the nook.Type: GrantFiled: February 6, 2015Date of Patent: April 11, 2017Assignees: STMICROELECTRONICS (MALTA) LTD, STMICROELECTRONICS S.R.L., STMICROELECTRONICS PTE LTDInventors: Roseanne Duca, Valter Motta, Xueren Zhang, Kim-Yong Goh
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Patent number: 9576912Abstract: A wafer level chip scale package (WLCSP) includes a semiconductor substrate, a back end of line (BEOL) layer on the semiconductor substrate and having a peripheral edge recessed inwardly from an adjacent peripheral edge of the semiconductor substrate. A first dielectric layer is over the BEOL layer and wraps around the peripheral edge of the BEOL layer. A redistribution layer is over the first dielectric layer and a second dielectric layer is over the redistribution layer.Type: GrantFiled: December 3, 2015Date of Patent: February 21, 2017Assignee: STMICROELECTRONICS PTE LTDInventors: Yiyi Ma, Kim-Yong Goh, Xueren Zhang
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Publication number: 20160293512Abstract: An electronic device may include a substrate, an active IC die above the substrate, and a dummy IC die above the active IC die. The electronic device may include a first adhesive layer between the active IC die and the dummy IC die, and a heat sink layer above the dummy IC die and extending laterally outwardly to define a gap between the substrate and opposing portions of the heat sink layer.Type: ApplicationFiled: March 31, 2015Publication date: October 6, 2016Inventors: Yiyi MA, Kim-Yong GOH, Xueren ZHANG
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Patent number: 9449912Abstract: An integrated circuit (IC) module for an IC card includes a plurality of IC card contacts in side-by-side relation. A dielectric support layer is above the contact layer and has a plurality of openings and a first coefficient of thermal expansion (CTE). An IC die is above the dielectric support layer and includes a plurality of bond pads. A bond wire extends from a respective bond pad to a corresponding contact through an adjacent opening in the dielectric support layer. A respective body of fill material is within each opening and has a second CTE. A mold compound body is above the dielectric support layer, the bodies of fill material, and surrounding the IC die. The mold compound body has a third CTE. The first CTE is closer to the second CTE than to the third CTE.Type: GrantFiled: June 11, 2015Date of Patent: September 20, 2016Assignees: STMICROELECTRONICS PTE LTD, STMICROELECTRONICS (MALTA) LTDInventors: Xueren Zhang, Kim-Yong Goh, Roseanne Duca
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Publication number: 20160190029Abstract: A method of making an electronic device may include positioning an integrated circuit (IC) die on an upper surface of a grid array substrate having connections on a lower surface thereof and coupling respective bond pads of the IC die to the grid array with bond wires. The method may also include forming a first encapsulating layer over the IC die and bond wires and positioning a heat spreader on the substrate above the first encapsulating layer after forming the first encapsulating layer. The method may further include forming a second encapsulating layer over the first encapsulating layer and embedding the heat spreader in the second encapsulating layer.Type: ApplicationFiled: December 30, 2014Publication date: June 30, 2016Inventors: Kim-Yong GOH, Yiyi Ma, Xueren Zhang
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Patent number: 9379034Abstract: A method of making an electronic device may include positioning an integrated circuit (IC) die on an upper surface of a grid array substrate having connections on a lower surface thereof and coupling respective bond pads of the IC die to the grid array with bond wires. The method may also include forming a first encapsulating layer over the IC die and bond wires and positioning a heat spreader on the substrate above the first encapsulating layer after forming the first encapsulating layer. The method may further include forming a second encapsulating layer over the first encapsulating layer and embedding the heat spreader in the second encapsulating layer.Type: GrantFiled: December 30, 2014Date of Patent: June 28, 2016Assignee: STMICROELECTRONICS PTE LTDInventors: Kim-Yong Goh, Yiyi Ma, Xueren Zhang
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Publication number: 20160172262Abstract: An integrated circuit (IC) device includes an IC and encapsulating material surrounding the IC. Leads are coupled to the IC and extend outwardly from sides of the encapsulating material, with each lead having three contiguous exposed segments with upper and lower bends defining a Z-shape. In another example, the leads include an upper horizontal segment, lower horizontal segment, and intermediate curved segment extending upwardly from the upper horizontal segment and downwardly to the lower horizontal segment.Type: ApplicationFiled: December 10, 2014Publication date: June 16, 2016Inventors: Yiyi MA, Kim-Yong GOH, Xueren ZHANG, Wei Zhen GOH
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Patent number: 9257372Abstract: A surface mount package of a semiconductor device, has: an encapsulation, housing at least one die including semiconductor material; and electrical contact leads, protruding from the encapsulation to be electrically coupled to contact pads of a circuit board; the encapsulation has a main face designed to face a top surface of the circuit board, which is provided with coupling features designed for mechanical coupling to the circuit board to increase a resonant frequency of the mounted package. The coupling features envisage at least a first coupling recess defined within the encapsulation starting from the main face, designed to be engaged by a corresponding coupling element fixed to the circuit board, thereby restricting movements of the mounted package.Type: GrantFiled: September 19, 2013Date of Patent: February 9, 2016Assignees: STMicroelectronics (Mala) Ltd, STMicroelectronics Pte LtdInventors: Roseanne Duca, Kim-Yong Goh, Xueren Zhang, Kevin Formosa
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Publication number: 20150332995Abstract: An electronic device may include a surface mount integrated circuit (IC) package to be attached to a printed circuit board (PCB). The surface mount IC package may include at least one IC and an encapsulating material surrounding the at least one IC and having a component receiving cavity defined therein on a bottom surface thereof to be positioned adjacent the PCB. The surface mount IC package may also include electrical leads coupled to the at least one IC and extending outwardly from the encapsulating material to be coupled to the PCB. The electronic device may also include at least one electronic component carried within the component receiving cavity and that includes electrical contacts to be coupled to the PCB.Type: ApplicationFiled: May 15, 2014Publication date: November 19, 2015Applicant: STMICROELECTRONICS PTE LTDInventors: Kim-Yong GOH, Wing Shenq Wong
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Publication number: 20150235929Abstract: An electronic device includes an integrated circuit chip mounted to a heat slug. The heat slug has a peripheral region having first thickness along a first direction, the peripheral region surrounding a recess region (having a second, smaller, thickness along the first direction) that defines a chip mounting surface along a second direction perpendicular to the first direction. The recess region defines side borders and a nook extends into the heat slug along the side borders. An insulating body embeds the integrated circuit one chip and heat slug. Material of the insulating body fills the nook.Type: ApplicationFiled: February 6, 2015Publication date: August 20, 2015Applicants: STMICROELECTRONICS (MALTA) LTD, STMICROELECTRONICS S.R.L., STMICROELECTRONICS PTE LTDInventors: Roseanne Duca, Valter Motta, Xueren Zhang, Kim-Yong Goh
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Publication number: 20150084171Abstract: A non-lead (QFN) semiconductor package is disclosed. The package includes a die attach pad and a semiconductor die supported by the die attached pad. The semiconductor die includes a plurality of pads on an active surface thereof. The package further includes a plurality of terminal leads, an encapsulant that encapsulates the semiconductor die, and a redistribution layer including a plurality of interconnections electrically connecting the pads to the terminal leads. A method of making the package is also disclosed.Type: ApplicationFiled: September 23, 2013Publication date: March 26, 2015Applicant: STMicroelectronics Pte. Ltd.Inventors: Yiyi Ma, Kim-Yong Goh, Xueren Zhang
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Patent number: 8907465Abstract: Methods and devices for packaging integrated circuits. A packaged device may include an integrated circuit, a first packaging component including a patterned surface, and a second packaging component. The patterned surface of the first packaging component may be adhesively coupled to a surface of the second packaging component or a surface of the integrated circuit. The integrated circuit may be at least partially enclosed between the first and second packaging components. A packaging method may include patterning a surface of a packaging component of an integrated circuit package. The surface of the packaging component may be for adhesively coupling to a second component to at least partially enclose an integrated circuit in the integrated circuit package.Type: GrantFiled: March 29, 2013Date of Patent: December 9, 2014Assignee: STMicroelectronics Pte LtdInventors: Kim-Yong Goh, Yiyi Ma, Wei Zhen Goh
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Flip-chip fan-out wafer level package for package-on-package applications, and method of manufacture
Patent number: 8884422Abstract: A flip-chip fan-out wafer level package for package-on-package applications includes a semiconductor die with solder bumps on an upper surface in a flip chip configuration. The die is inverted, with an upper surface facing an upper side of a redistribution layer, with the solder bumps in electrical contact with respective chip contact pads of the redistribution layer. The redistribution layer includes conductive traces that place each of the solder bumps in electrical contact with one or both of one of a plurality of upper redistribution contact pads and one of a plurality of lower redistribution contact pads. Each of the plurality of upper redistribution contact pads has an upper solder ball in electrical contact therewith. The die and the upper solder balls are at least partially encapsulated in a layer of mold compound positioned on the upper surface of the redistribution layer, and whose lateral dimensions are defined by the lateral dimensions of the redistribution layer.Type: GrantFiled: December 31, 2009Date of Patent: November 11, 2014Assignee: STMicroelectronics Pte Ltd.Inventors: Kim-Yong Goh, Jing-En Luan -
Publication number: 20140291782Abstract: Methods and devices for packaging integrated circuits. A packaged device may include an integrated circuit, a first packaging component including a patterned surface, and a second packaging component. The patterned surface of the first packaging component may be adhesively coupled to a surface of the second packaging component or a surface of the integrated circuit. The integrated circuit may be at least partially enclosed between the first and second packaging components. A packaging method may include patterning a surface of a packaging component of an integrated circuit package. The surface of the packaging component may be for adhesively coupling to a second component to at least partially enclose an integrated circuit in the integrated circuit package.Type: ApplicationFiled: March 29, 2013Publication date: October 2, 2014Applicant: STMicroelectronics Pte Ltd.Inventors: Kim-Yong Goh, Yiyi Ma, Wei Zhen Goh
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Publication number: 20140291812Abstract: Embodiments are directed to a package that includes an electric device having a recess. In one embodiment, the electric device is a sensor and the recess reduces signal drift of the sensor caused by thermal expansion of the package. In another embodiment, the recess is substantially filled with adhesive material, thus increasing adhesion between the electric device and a substrate of the package while at the same time allowing for lower adhesive fillets.Type: ApplicationFiled: March 29, 2013Publication date: October 2, 2014Applicant: STMicroelectronics Pte Ltd.Inventors: Kim-Yong Goh, Xueren Zhang, Yiyi Ma
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Patent number: 8822267Abstract: Embodiments of the present disclosure are related to manufacturing system-in-packages at wafer-level. In particular, various embodiments are directed to adhering a first wafer to a second wafer and adhering solder balls to contact pads of the first wafer. In one embodiment, a first wafer having first and second surfaces is provided. The first wafer includes bond pads located on the first surface that are coupled to a respective semiconductor device located in the first wafer. A second wafer having an electrical component located therein is provided. A conductive adhesive is provided on at least one of the first wafer and the second wafer. Conductive balls are provided on the bond pads on the first surface of the first wafer. The conductive balls and the conductive adhesive are heated to cause the conductive balls to adhere to the bond pad and the conductive adhesive to adhere the first wafer to the second wafer.Type: GrantFiled: October 18, 2012Date of Patent: September 2, 2014Assignee: STMicroelectronics Pte Ltd.Inventors: How Yuan Hwang, Jay Maghirang, Yaohuang Huang, Kim-Yong Goh, Phone Maw Hla, Edmond Soon