Patents by Inventor Kimiaki Satoh

Kimiaki Satoh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Semiconductor memory device having an SRAM and a DRAM on a single chip
    Patent number: 6735141
    Abstract: A semiconductor memory device includes an SRAM provided on a chip, the SRAM including an SRAM cell array. A DRAM is provided on the chip, the DRAM including a DRAM cell array. An address input circuit receives an address signal, the address signal having a first portion and a second portion, the first portion carrying a unique value of row-column address information provided to access one of memory locations in one of the SRAM and DRAM cell arrays, the second portion carrying a unique value of SRAM/DRAM address information provided to select one of the SRAM and the DRAM.
    Type: Grant
    Filed: July 31, 2001
    Date of Patent: May 11, 2004
    Assignee: Fujitsu Limited
    Inventors: Hitoshi Ikeda, Akihiro Funyu, Shinya Fujioka, Takaaki Suzuki, Masao Taguchi, Kimiaki Satoh, Kotoku Sato
  • Semiconductor memory device and electronic apparatus
    Patent number: 6724675
    Abstract: A semiconductor memory device, such as a DRAM, which needs to be refreshed for retaining data, is provided with a storing portion for storing data therein, and a busy signal outputting portion outputting a busy signal during the refresh operation.
    Type: Grant
    Filed: January 29, 2003
    Date of Patent: April 20, 2004
    Assignee: Fujitsu Limited
    Inventors: Akihiro Funyu, Shinya Fujioka, Hitoshi Ikeda, Takaaki Suzuki, Masao Taguchi, Kimiaki Satoh, Kotoku Sato, Yasurou Matsuzaki
  • Semiconductor memory device and electronic apparatus
    Publication number: 20030115405
    Abstract: A semiconductor memory device, such as a DRAM, which needs to be refreshed for retaining data, is provided with a storing portion for storing data therein, and a busy signal outputting portion outputting a busy signal during the refresh operation.
    Type: Application
    Filed: January 29, 2003
    Publication date: June 19, 2003
    Applicant: Fujitsu Limited
    Inventors: Akihiro Funyu, Shinya Fujioka, Hitoshi Ikeda, Takaaki Suzuki, Masao Taguchi, Kimiaki Satoh, Kotoku Sato, Yasurou Matsuzaki
  • Semiconductor memory device having a refresh operation
    Patent number: 6535950
    Abstract: A semiconductor memory device, such as a DRAM, which needs to be refreshed for retaining data, is provided with a storing portion for storing data therein, and a busy signal outputting portion outputting a busy signal during the refresh operation.
    Type: Grant
    Filed: March 29, 2000
    Date of Patent: March 18, 2003
    Assignee: Fujitsu Limited
    Inventors: Akihiro Funyu, Shinya Fujioka, Hitoshi Ikeda, Takaaki Suzuki, Masao Taguchi, Kimiaki Satoh, Kotoku Sato, Yasurou Matsuzaki
  • DRAM for storing data in pairs of cells
    Patent number: 6344990
    Abstract: A memory circuit including a memory cell array. The memory cell array has a first word line group connected to a pair of memory cells associated with a first bit line pair including first and third bit lines, and a second word line group, connected to a pair of memory cells associated with a second bit line pair including second and fourth bit lines. First and second sense amplifier groups are positioned one on each side of the memory array, and are connected to the first and second bit line pair, respectively. When any word line of the first word line group is driven, the first sense amplifier group is activated to drive the first word line group in reverse phase, and the second sense amplifier group is kept in the inactive state to keep the second word line group at the precharge level.
    Type: Grant
    Filed: August 31, 2000
    Date of Patent: February 5, 2002
    Assignee: Fujitsu Limited
    Inventors: Masato Matsumiya, Shinya Fujioka, Kimiaki Satoh, Toru Miyabo
  • Semiconductor memory device having an SRAM and a DRAM on a single chip
    Publication number: 20020006071
    Abstract: A semiconductor memory device includes an SRAM provided on a chip, the SRAM including an SRAM cell array. A DRAM is provided on the chip, the DRAM including a DRAM cell array. An address input circuit receives an address signal, the address signal having a first portion and a second portion, the first portion carrying a unique value of row-column address information provided to access one of memory locations in one of the SRAM and DRAM cell arrays, the second portion carrying a unique value of SRAM/DRAM address information provided to select one of the SRAM and the DRAM.
    Type: Application
    Filed: July 31, 2001
    Publication date: January 17, 2002
    Applicant: Fujitsu Limited
    Inventors: Hitoshi Ikeda, Akihiro Funyu, Shinya Fujioka, Takaaki Suzuki, Masao Taguchi, Kimiaki Satoh, Kotoku Sato
  • Semiconductor memory device having an SRAM and a DRAM on a single chip
    Patent number: 6292426
    Abstract: A semiconductor memory device includes an SRAM provided on a chip, the SRAM including an SRAM cell array. A DRAM is provided on the chip, the DRAM including a DRAM cell array. An address input circuit receives an address signal, the address signal having a first portion and a second portion, the first portion carrying a unique value of row-column address information provided to access one of memory locations in one of the SRAM and DRAM cell arrays, the second portion carrying a unique value of SRAM/DRAM address information provided to select one of the SRAM and the DRAM.
    Type: Grant
    Filed: March 21, 2000
    Date of Patent: September 18, 2001
    Assignee: Fujitsu Limited
    Inventors: Hitoshi Ikeda, Akihiro Funyu, Shinya Fujioka, Takaaki Suzuki, Masao Taguchi, Kimiaki Satoh, Kotoku Sato