Abstract: Distributively associated with each output row of point cells or each subset of point cells in each output row is one or more of a: memory device for storing an address identifying a cell in its associated output row and a decoder device responsive to the memory device for actuating the associated enable circuit to operate the transconductance device of the identified cell; a bias device, and an output cascode device; and also disclosed as switching systems having a bias device including a current mirror with an input reference portion responsive to a reference current and a co-located output local portion for reproducing that current as the bias current.

Abstract: In embodiments of the present invention, the problems of poor low-frequency response, slow speed, high cost and high power consumption in conventional voltage translators are addressed by processing high frequency and low frequency components of an input signal separately in two parallel stages without the use of large passive components or slow devices. At the output, the processed high frequency and low frequency components are seamlessly merged at a combining stage that maintains the integrity of the frequency response over the complete translator bandwidth.

Abstract: A dual core crosspoint system includes a differential signal core for receiving N differential input channels with common mode voltage removed and providing m differential output channels with m output stages associated with the m output channels; and a common mode core for receiving N common mode voltage input channels derived from the N differential input channels and providing m common mode voltage output channels simultaneously with the m differential output channels.

Abstract: An impedance matched lane reversal switching system including first and second transceiver pairs, each of the pairs including a transmitter connected to a receiver, the output of the transmitter connected to the input of the receiver and to a node, the node of each pair interconnected with a transmission line and a switching circuit for selectively enabling one of the transmitters of one of the transceiver pairs and disabling the other and selectively utilizing one of the receivers of the other of the transceiver pairs and not the other to selectively reverse an egress side and an ingress side of the lane.

Abstract: In embodiments of the present invention, the problems of poor low-frequency response, slow speed, high cost and high power consumption in conventional voltage translators are addressed by processing high frequency and low frequency components of an input signal separately in two parallel stages without the use of large passive components or slow devices. At the output, the processed high frequency and low frequency components are seamlessly merged at a combining stage that maintains the integrity of the frequency response over the complete translator bandwidth.

Abstract: An impedance matched lane reversal switching system including first and second transceiver pairs, each of the pairs including a transmitter connected to a receiver, the output of the transmitter connected to the input of the receiver and to a node, the node of each pair interconnected with a transmission line and a switching circuit for selectively enabling one of the transmitters of one of the transceiver pairs and disabling the other and selectively utilizing one of the receivers of the other of the transceiver pairs and not the other to selectively reverse an egress side and an ingress side of the lane.

Abstract: An amplifier structure includes shield conductors that are provided spatially adjacent to elongated feedback signal lines that couple a feedback circuit to an amplifier input. The shield conductors are provided between the feedback signal lines and a ground plane, which interrupts a parasitic capacitance that otherwise would be established between the feedback signal line and ground. The shield conductors are electrically coupled to the amplifier's outputs which create a capacitance between the output terminal and the feedback signal line. In some embodiments, the capacitance generated between the output terminal and the feedback signal line can suffice as a capacitor in a feedback path of the amplifier and be contained in an integrated circuit die on which the amplifier is manufactured. Optionally, a structure may be provided that eliminates common mode signals on the feedback lines while simultaneously preserving the common mode signals on the amplifier output terminals.

Abstract: Disclosed are a circuit and a method for tuning a programmable filter including input terminals, output terminals, a filter network and a transadmittance stage. The input terminals can receive input signals, and the output terminals output a filtered signal. The transadmittance stage, coupled to the input terminals, generates a current at its output based on the input signals. The output of the transadmittance stage can be coupled to the output terminals. The filter network can be a resistive-capacitive network connected to the input terminals. The RC network can include a capacitance respectively coupling the input terminals to output terminals, and a voltage divider network coupling the input and output terminals together. The transadmittance stage output terminals can be connected to the voltage divider, and the output terminals of the programmable filter circuit are coupled to respective intermediate nodes of the voltage divider network to provide a filtered output signal.

Abstract: A method of operating a circuit for processing a digital signal is disclosed. The circuit includes various circuit stages having respective enabled states. A present signal path is established which includes circuit stages in their respective enabled states. Power is disabled to selected circuit stages not used in the present signal path so as to minimize power consumption in the disabled circuit stages. A data signal is then processed through the circuit stages in the present signal path. Before a next signal path is needed, power is re-enabled to selected disabled circuit stages in the next signal path to allow the enabled circuit stages to approach their respective enabled states. Then the next signal path can be established including the enabled circuit stages in their respective enabled states. The data signal can then be processed through the circuit stages in the next signal path.

Abstract: A redundant cross point switching is achieved by mapping a redundant column/row of point cells and enabling at least one of the switching devices which is associated with each column/row to define an alternate path around the defective point cell which replicates the function of the switching location of the defective point cell.

Abstract: Disclosed is a differential amplifier system that maintains high speed characteristics of the differential amplifier while providing stability from a common-mode loop by using dominant pole compensation. The disclosed system includes a first and second transconductance stage, a circuit having high impedance, and a compensation circuit.

Abstract: A balanced, differential, cross-coupled amplifier including an input stage for receiving a differential input and including an input transconductance differential pair and a feedback transconductance differential pair; and an output stage responsive to the input stage for providing a differential output; the differential input being connected to one input of the input transconductance differential pair and one input of the feedback transconductance differential pair, the differential output being fed back to one input of the input transconductance differential pair and one input of the feedback transconductance differential pair for balancing the currents in the transconductance differential pairs over the input range.

Abstract: Disclosed is a differential amplifier system that maintains high speed characteristics of the differential amplifier while providing stability from a common-mode loop by using dominant pole compensation. The disclosed system includes a first and second transconductance stage, a circuit having high impedance, and a compensation circuit.

Abstract: Disclosed are a circuit and a method for tuning a programmable filter including input terminals, output terminals, a filter network and a transadmittance stage. The input terminals can receive input signals, and the output terminals output a filtered signal. The transadmittance stage, coupled to the input terminals, generates a current at its output based on the input signals. The output of the transadmittance stage can be coupled to the output terminals. The filter network can be a resistive-capacitive network connected to the input terminals. The RC network can include a capacitance respectively coupling the input terminals to output terminals, and a voltage divider network coupling the input and output terminals together. The transadmittance stage output terminals can be connected to the voltage divider, and the output terminals of the programmable filter circuit are coupled to respective intermediate nodes of the voltage divider network to provide a filtered output signal.

Abstract: A balanced, differential, cross-coupled amplifier including an input stage for receiving a differential input and including an input transconductance differential pair and a feedback transconductance differential pair; and an output stage responsive to the input stage for providing a differential output; the differential input being connected to one input of the input transconductance differential pair and one input of the feedback transconductance differential pair, the differential output being fed back to one input of the input transconductance differential pair and one input of the feedback transconductance differential pair for balancing the currents in the transconductance differential pairs over the input range.

Abstract: A dual core crosspoint system includes a differential signal core for receiving N differential input channels with common mode voltage removed and providing m differential output channels with m output stages associated with the m output channels; and a common mode core for receiving N common mode voltage input channels derived from the N differential input channels and providing m common mode voltage output channels simultaneously with the m differential output channels.

Abstract: A redundant cross point switching is achieved by mapping a redundant column/row of point cells and enabling at least one of the switching devices which is associated with each column/row to define an alternate path around the defective point cell which replicates the function of the switching location of the defective point cell.

Abstract: Distributively associated with each output row of point cells or each subset of point cells in each output row is one or more of a: memory device for storing an address identifying a cell in its associated output row and a decoder device responsive to the memory device for actuating the associated enable circuit to operate the transconductance device of the identified cell; a bias device, and an output cascode device; and also disclosed as switching systems having a bias device including a current mirror with an input reference portion responsive to a reference current and a co-located output local portion for reproducing that current as the bias current.

Abstract: A margin tracking cascode current mirror system including a current mirror circuit having a current source device having a predetermined operating voltage for providing a current to a load, a cascode circuit interconnected between the current mirror and the load for controlling the output impedance of the system and for establishing a current control voltage, a cascode bias circuit for providing a forward bias to the cascode circuit, and a compound cascode bias circuit for independently controlling the slope and the offset of the current control voltage to track the predetermined operating voltage with a predetermined margin.

Abstract: A circuit for a high speed digital buffer has an active load circuit connected to an output of the digital buffer. The active load circuit loads the buffer output with an active inductance to reduce the RC time constant at the buffer output. The active load circuit may be based on two active devices connected to the buffer output so as to form a differential cascode circuit.