Abstract: A local host data processing system operating under the control of a local host operating system includes components of multiple emulating hosted operating systems. The host operating system further include a TCP/IP network protocol stack which couples to the communications facilities of the host system connected to a local area network for communicating with a number of remote host systems. Host and hosted operating systems share the same TCP/IP network protocol stack. A virtual network mechanism is configured within the local host system to be operatively coupled to the host network protocol stack and provide access to well-known port application programs. When so configured, the mechanism functions as another LAN to which multiple virtual host systems are attached for executing applications under control of the emulating hosted operating systems.

Abstract: A host data processing system operating under the control of a host operating system such as an enhanced version of the UNIX operating system on a RISC based hardware platform includes an emulator which runs as an application process for executing emulated system (ES) user application programs. The emulator includes a number of emulated system executive service components including a socket command handler unit and a socket library component operating in shared memory and an interpreter, an emulator monitor call unit (EMCU) and a number of server components operating in host memory. The host operating system further includes a host socket library interface layer (API) which operatively connects through a TCP/IP network protocol stack to the communications facilities of the hardware platform. The socket server components operatively connect ES TCP/IP application programs to the socket library interface layer of the host operating system when such application programs issue standard ES socket library calls.

Abstract: A host data processing system which includes a plurality of input/output devices operates under the control of an enhanced version of the UNIX operating system. The host system includes an emulator which runs as an application process for executing user emulated system (ES) application programs. The emulator includes a number of emulated system executive service components operating in shared memory and an interpreter, an emulator monitor call unit (EMCU) and a number of server facilities operating in the host memory. The ES executive service command handler component is extended to accommodate a number of dual decor commands which invoke host system facilities to execute terminal based commands either synchronously or asynchronously through the automatic creation of host shell mechanisms directly accessible by emulated system users. The server facilities include a network terminal driver (NTD) server for executing emulated system user terminal requests through host system drivers.

Abstract: A local host data processing system operating under the control of a local host operating system includes components of a hosted operating system. The host operating system further include a TCP/IP network protocol stack which couples to the communications facilities of the host system connected to a local area network for communicating with a number of remote host systems. Host and hosted operating systems share the same TCP/IP network protocol stack. A virtual network mechanism is configured within the local host system to be operatively coupled to the host network protocol stack and provide access to well-known port application programs. When so configured, the mechanism functions as another LAN to which the hosted operating system is attached. The mechanism transforms the well-known port identifier of each inbound packet into a non-well-known port identifier in addition to other station address identifier fields.

Abstract: A hybrid system environment includes a proprietary operating system and processing unit and a non-proprietary operating system (UNIX based) and processing unit. The systems tightly couple to a system bus in common with a main memory and a number of multiline communications controllers and communicate through a common area of main memory. The UNIX terminal connections to such controllers are virtual connections applied by a virtual terminal driver through the system proprietary communications software components. These components include a server, a network terminal driver (NTD) and a number of multiplexer driver modules. A multiplexer physical terminal driver is included in the UNIX-based operating system and a switching mechanism is incorporated into the virtual terminal driver for enabling switching to such physical terminal driver when a user switches via a switch command to the UNIX-based operating system.

Abstract: A hybrid system environment includes a proprietary operating system and processing unit and a non-proprietary operating system (UNIX based) and processing unit tightly coupled to a system bus in common with a main memory and a plurality of controllers which include a number of multiline communications controllers and communicates through a common area of main memory. Terminal connections to the communications controllers for virtual terminal processing are made through a UNIX virtual terminal driver and system proprietary communications software components which include a server, network terminal driver (NTD) and multiplexer driver modules. The UNIX based operating system further includes a multiplexer terminal driver and a switching mechanism which is included within the virtual terminal driver. The mechanism enables switching from virtual terminal processing to direct terminal processing wherein communications is established between the multiplexer terminal driver and the communications controllers.

Abstract: A multiprocessor interrupt rerouting mechanism and method is disclosed for rerouting messages intended for a first processor to a second processor. In a fault tolerant computer system having several processors or LANs under the control of a single controller, when the controller completes a communication task requested by one of the processors, it will send an interrupt request to the requesting processor which then notifies the application process for which the communication task was performed, information regarding the status of the communication task. If for any reason the requesting processor being interrupted is inoperative or too busy to handle the interrupt request, the application process is then notified as to the status of the communication task by rerouting the interrupt request from the controller so that another processor can handle it.

Abstract: A data processing system includes a cathode ray tube (CRT) display. Apparatus associated with the CRT tests and verifies the vertical and horizontal synchronization and the logic associated with a character generator. Refresh signals, horizontal synchronization signals and data bit signals from the character generator are counted. The counts of those signals which occur within a predetermined number of occurrences of vertical synchronization signals are verified.

Abstract: A data processing system includes a communication subsystem having an I/O microprocessor for communicating with a central processing unit and a main memory; and a line microprocessor for communicating with a number of devices. The I/O microprocessor and the line microprocessor communicate with each other through mailboxes stored in a shared memory. The line microprocessor interrupts the I/O microprocessor to process data bytes being transferred between main memory and a device requesting service when the line microprocessor has responded to the requesting device and loaded the mailbox.

Abstract: A data processing system includes a central processing unit, a main memory, and a communication subsystem servicing a number of communication lines. The communication subsystem includes a free running timer, a line microprocessor for communicating with the communication lines and a shared memory, and an I/O microprocessor for communicating with the shared memory and the central processing unit and main memory. The line microprocessor, desiring to communicate with a specified communication line after a predetermined time delay, loads a first mailbox in shared memory with a binary number indicative of the predetermined time delay. The I/O microprocessor adds the output of the free running timer to the binary number, stores the result in a location in a random access memory, and periodically compares the result against the free running timer output. The I/O microprocessor loads a second mailbox with a control character when the results of the comparison indicate that the predetermined time delay is accomplished.

Abstract: A data processing system includes a central processing subsystem, a main memory subsystem, and a number of peripheral subsystems including a communication subsystem all coupled in common to a system bus. Subsystems communicate with each other during asynchronously generated information bus transfer cycles. Each one of the subsystems receives information by providing any one of three signal responses including a positive acknowledge signal indicating an immediate response, a negative acknowledge signal indicating that the unit will most likely be busy for an extended period of time, and a quasi-negative response indicating that the unit will probably be ready during the next asynchronously generated bus transfer cycle.

Abstract: A data processing system includes a number of input/output devices coupled to a communication multiplexer by 1 synchronous communication line and a number of asynchronous communication lines. During the polling operation, receive communication lines have high priority and transmit communication lines have low priority. Apparatus in the polling logic gives the synchronous communication line in the receive mode first priority and the synchronous communication line in the transmit mode second priority.

Abstract: A programmable communications processor is coupled to execute instructions of programs designed to process the transfer of information between a plurality of communication channels and a main memory included in the system. A software implemented and controlled pause counter enables the execution of a given maximum number of instructions for servicing, for example, a communication channel following which it suspends or pauses such servicing, in order to service another higher priority request which may be pending. Processing of lower priority service requests thus cannot delay the recognition and handling of higher priority requests for more than a minimum period of time and the effective throughput rate is increased.

Abstract: Firmware generated commands provided by a control store in a microprogrammed communications processor which is coupled in a system including a main memory and a central processing unit control the processing of instructions from the central processing unit, interrupts from the communications channels and servicing of such channels if a channel status change is detected. The firmware also controls the operation of the servicing of such channels by providing a control mechanism by which data is read from or written into the main memory. Further, interrupts which are not handled immediately are handled in a deferred interrupt arrangement.

Abstract: A paging apparatus includes addressing hardware for addressing a number of physical devices coupled to various communication buses, for mapping virtual addresses to real addresses, and controlling the flow of data. The paging apparatus generates 8 control signals, 5 of which modify a virtual address into a real address of a memory thereby expanding the capabilities of the real address from 256 address locations by an additional 512 address locations. The remaining 3 control signals control the flow of data by enabling or disabling data control apparatus in the physical devices.

Abstract: A remote maintenance apparatus for performing maintenance via a communication channel. Hardware is provided to retain information in a special channel which can be accessed by a remote communication system, in the event of malfunction in the computer system. An additional feature of this hardware is increased speed and efficiency in addressing when the computer system is operating normally.

Abstract: A multi-way vectored interrupt automatically addresses any one of a plurality of locations in a memory according to a unique function code. Hardware is provided which disables the normal paging addressing apparatus of a processor and enables an indirect addressing mechanism when a predetermined location in memory is addressed.