Abstract: Motion estimation in video compressions systems. A programmable motion estimator may be used to estimate a motion vector for a macroblock in a current frame by searching for a matching macroblock in a previous frame. A controller may be used to program the motion estimator to perform a particular search.

Abstract: A system and method that enhance the performance of cochlear implant signal processing in an amplification device. The system utilizes a signal input device that picks up the sounds from the environment or from other hearing or audio devices and feeds the incoming signal into a front-end signal processor, which can be signal processors from hearing aids, hearing protectors or other audio devices. The front-end processor preprocesses the signals and feeds them into a cochlear implant signal processor. The front-end processor may have multiple signal feeding and signal extraction points, other than the two ends, to which connections can be made to feed signals into and extract signals from the front-end processor. The system may also insert a front-end processor into multiple signal processing stages of a cochlear implant signal processor with the front-end processor “sandwiched” between the multiple signal processing stages of the cochlear implant signal processors.

Abstract: This disclosure describes video encoding techniques capable of reducing the number of processing cycles and memory transfers necessary to encode a video sequence. In this manner, the disclosed video encoding techniques may increase video encoding speed and reduce power consumption. In general, the video encoding techniques make use of a candidate memory that stores video blocks in columns corresponding to a search space for a motion estimation routine. A memory control unit addresses the candidate memory to retrieve multiple pixels in parallel for simultaneous comparison to pixels in a video block to be encoded, e.g., using Sum of Absolute Difference (SAD) or Sum of Squared Difference (SSD) techniques. A difference processor performs the parallel calculations. In addition, for subsequent video blocks to be encoded, the candidate memory can be incrementally updated by loading a new column of video blocks, rather than reloading the entire search space.

Abstract: This disclosure describes video encoding techniques capable of reducing the number of processing cycles and memory transfers necessary to encode a video sequence. In this manner, the disclosed video encoding techniques may increase video encoding speed and reduce power consumption. In general, the video encoding techniques make use of a candidate memory that stores video blocks in columns corresponding to a search space for a motion estimation routine. A memory control unit addresses the candidate memory to retrieve multiple pixels in parallel for simultaneous comparison to pixels in a video block to be encoded, e.g., using Sum of Absolute Difference (SAD) or Sum of Squared Difference (SSD) techniques. A difference processor performs the parallel calculations. In addition, for subsequent video blocks to be encoded, the candidate memory can be incrementally updated by loading a new column of video blocks, rather than reloading the entire search space.

Abstract: This disclosure is directed to encoding techniques that can be used to improve encoding of digital video data. The techniques can be implemented by an encoder of a digital video device in order to reduce the number of computations and possibly reduce power comsumption during video encoding. More specifically, video encoding techniques are describe which utilize one or more programmable thresholds in order to terminate the execution of various computations when the computations would be unlikely to improve the encoding. By terminating computations prematurely, the amount of processing required for video encoding can be reduced, and power can be conserved.