Abstract: A method and an apparatus to reduce duty cycle distortion are described. The apparatus may include a first current-mode logic (CML) circuit block comprising a positive input and a negative input and a second CML circuit block coupled in series to the first CML circuit block. The second CML circuit block may comprise a positive output, a negative output and a first transistor coupled between the positive input and the positive output. The second transistor may be coupled between the negative input and the negative output of the second CML circuit block.

Abstract: In one embodiment, a control loop in an electrical circuit includes a variable feed-forward circuit configured to determine a setting of a variable oscillator that would result in a frequency of a first signal approximating a frequency of a second signal. The setting may be used to control the variable oscillator at a time when a phase error between the first signal and the second signal is negligibly small (e.g., substantially zero), thus allowing for relatively short loop convergence time.