Patents by Inventor King W. Chan
King W. Chan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8990757Abstract: An interface design for a hybrid IC that utilizes dedicated interface tracks to allow signals to interface distributively with the logic blocks of the FPGA portion providing for faster and more efficient communication between the FPGA and ASIC portions of the hybrid IC.Type: GrantFiled: May 2, 2008Date of Patent: March 24, 2015Assignee: Microsemi SoC CorporationInventors: King W. Chan, William C. T. Shu, Sinan Kaptanoglu, Chi Fung Cheng
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Patent number: 8258811Abstract: An enhanced performance field programmable gate array integrated circuit comprises a field programmable gate array and other functional circuitry such as a mask-programmable gate array in the same integrated circuit. A circuit interface provides communication between the field programmable gate array, the mask-programmable gate array and the integrated circuit I/O.Type: GrantFiled: June 10, 2011Date of Patent: September 4, 2012Assignee: Actel CorporationInventors: Samuel W. Beal, Sinan Kaptanoglu, Jung-Cheun Lien, William Shu, King W. Chan, William C. Plants
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Publication number: 20110234258Abstract: An enhanced performance field programmable gate array integrated circuit comprises a field programmable gate array and other functional circuitry such as a mask-programmable gate array in the same integrated circuit. A circuit interface provides communication between the field programmable gate array, the mask-programmable gate array and the integrated circuit I/O.Type: ApplicationFiled: June 10, 2011Publication date: September 29, 2011Applicant: ACTEL CORPORATIONInventors: Samuel W. Beal, Sinan Kaptonoglu, Jung-Cheun Lien, William Shu, King W. Chan, William C. Plants
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Patent number: 7977970Abstract: An enhanced performance field programmable gate array integrated circuit comprises a field programmable gate array and other functional circuitry such as a mask-programmable gate array in the same integrated circuit. A circuit interface provides communication between the field programmable gate array, the mask-programmable gate array and the integrated circuit I/O.Type: GrantFiled: June 4, 2010Date of Patent: July 12, 2011Assignee: Actel CorporationInventors: Samuel W. Beal, Sinan Kaptanoglu, Jung-Cheun Lien, William Shu, King W. Chan, William C. Plants
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Publication number: 20100244894Abstract: An enhanced performance field programmable gate array integrated circuit comprises a field programmable gate array and other functional circuitry such as a mask-programmable gate array in the same integrated circuit. A circuit interface provides communication between the field programmable gate array, the mask-programmable gate array and the integrated circuit I/O.Type: ApplicationFiled: June 4, 2010Publication date: September 30, 2010Inventors: Samuel W. Beal, Sinan Kaptanoglu, Jung-Cheun Lien, William Shu, King W. Chan, William C. Plants
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Patent number: 7755386Abstract: An enhanced performance field programmable gate array integrated circuit comprises a field programmable gate array and other functional circuitry such as a mask-programmable gate array in the same integrated circuit. A circuit interface provides communication between the field programmable gate array, the mask-programmable gate array and the integrated circuit I/O.Type: GrantFiled: April 29, 2008Date of Patent: July 13, 2010Assignee: Actel CorporationInventors: Samuel W. Beal, Sinan Kaptonoglu, Jung-Cheun Lien, William Shu, King W. Chan, William C. Plants
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Publication number: 20080204074Abstract: An interface design for a hybrid IC that utilizes dedicated interface tracks to allow signals to interface distributively with the logic blocks of the FPGA portion providing for faster and more efficient communication between the FPGA and ASIC portions of the hybrid IC.Type: ApplicationFiled: May 2, 2008Publication date: August 28, 2008Applicant: ACTEL CORPORATIONInventors: King W. Chan, William C.T. Shu, Sinan Kaptanoglu, Chi Fung Cheng
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Publication number: 20080197878Abstract: An enhanced performance field programmable gate array integrated circuit comprises a field programmable gate array and other functional circuitry such as a mask-programmable gate array in the same integrated circuit. A circuit interface provides communication between the field programmable gate array, the mask-programmable gate array and the integrated circuit I/O.Type: ApplicationFiled: April 29, 2008Publication date: August 21, 2008Applicant: ACTEL CORPORATIONInventors: Samuel W. Beal, Sinan Kaptonoglu, Jung-Cheun Lien, William Shu, King W. Chan, William C. Plants
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Patent number: 7389487Abstract: An interface design for a hybrid IC that utilizes dedicated interface tracks to allow signals to interface distributively with the logic blocks of the FPGA portion providing for faster and more efficient communication between the FPGA and ASIC portions of the hybrid IC.Type: GrantFiled: April 28, 1998Date of Patent: June 17, 2008Assignee: Actel CorporationInventors: King W. Chan, William C. T. Shu, Sinan Kaptanoglu, Chi Fung Cheng
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Patent number: 7382155Abstract: An enhanced performance field programmable gate array integrated circuit comprises a field programmable gate array and other functional circuitry such as a mask-programmable gate array in the same integrated circuit. A circuit interface provides communication between the field programmable gate array, the mask-programmable gate array and the integrated circuit I/O.Type: GrantFiled: August 10, 2004Date of Patent: June 3, 2008Assignee: Actel CorporationInventors: Samuel W. Beal, Sinan Kaptonoglu, Jung-Cheun Lien, William Shu, King W. Chan, William C. Plants
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Patent number: 6791353Abstract: An enhanced performance field programmable gate array integrated circuit comprises a field programmable gate array and other functional circuitry such as a mask-programmable gate array in the same integrated circuit. A circuit interface provides communication between the field programmable gate array, the mask-programmable gate array and the integrated circuit I/O.Type: GrantFiled: September 25, 2000Date of Patent: September 14, 2004Assignee: Actel CorporationInventors: Samuel W. Beal, Sinan Kaptonoglu, Jung-Cheun Lien, William Shu, King W. Chan, William C. Plants
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Patent number: 6678848Abstract: In a one-time programmable FPGA, new circuitry interfaces between boundary scan registers and configurable I/O cells is disclosed incorporating the use of boundary scan registers for both addressing, and establishing the value of, individual programmable elements used to configure configurable I/O.Type: GrantFiled: December 21, 2000Date of Patent: January 13, 2004Assignee: Actel CorporationInventor: King W. Chan
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Patent number: 6150837Abstract: An enhanced performance field programmable gate array integrated circuit comprises a field programmable gate array and other functional circuitry such as a mask-programmable gate array in the same integrated circuit. A circuit interface provides communication between the field programmable gate array, the mask-programmable gate array and the integrated circuit I/O.Type: GrantFiled: February 28, 1997Date of Patent: November 21, 2000Assignee: Actel CorporationInventors: Samuel W. Beal, Sinan Kaptonoglu, Jung-Cheun Lien, William Shu, King W. Chan, William C. Plants
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Patent number: 5936426Abstract: A logic function module comprises a plurality of input nodes and an output node. A first control circuit has at least one input connected to one of the input nodes, a first output, and a second output which is the complement of the first output. A second control circuit has at least one input connected to one of the input nodes, a first output, and a second output which is the complement of the first output. A first switching circuit is connected between one of the input nodes and the output node and is controlled from the first output of the first control circuit the first output of the second switching circuit. A second switching circuit is connected between one of the input nodes and the output node and is controlled from the second output of the first control circuit the first output of the second switching circuit.Type: GrantFiled: February 3, 1997Date of Patent: August 10, 1999Assignee: Actel CorporationInventors: Stanley Wilson, King W. Chan, Mark Frappier
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Patent number: 5804960Abstract: A circuit for providing 100% observability and controllability of inputs and outputs of any function circuit module in an array of function circuit modules includes circuitry for placing a test data bit into a selected one of any of the function circuit modules, and circuitry for reading the output of a selected one of any of the function circuit modules.Type: GrantFiled: September 27, 1996Date of Patent: September 8, 1998Assignee: Actel CorporationInventors: Khaled El Ayat, King W. Chan, Theodore M. Speers
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Patent number: 5698992Abstract: A user-programmable gate array architecture includes an array of logic function modules which may comprise one or more combinatorial and/or sequential logic circuits. An interconnect architecture comprising a plurality of horizontal and vertical general interconnect channels, each including a plurality of interconnect conductors some of which may be segmented, is imposed on the array. Individual ones of the interconnect conductors are connectable to each other and to the inputs and outputs of the logic function modules by user-programmable interconnect elements. A local interconnect architecture comprising local interconnect channels is also imposed on the array. Each local interconnect channel includes a plurality of local interconnect conductors and runs between pairs of adjacent ones of the logic function modules.Type: GrantFiled: November 13, 1996Date of Patent: December 16, 1997Assignee: Actel CorporationInventors: Khaled A. El Ayat, Gregory W. Bakker, Jung-Cheun Lien, William C. Plants, Sinan Kaptanoglu, Runip Gopisetty, King W. Chan, Marko Chew
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Patent number: 5625301Abstract: An input/output architecture for a field-programmable gate array integrated circuit including a plurality of logic function modules in an array of rows and columns, each of the modules having at least one input conductor and at least one output conductor; a plurality of interconnect conductors, comprising a plurality of input/output pads; a plurality of input/output kernels, each input/output kernel comprising an input buffer having a data input connected to one of the I/O pads and a data output connected to an input buffer data conductor, an output buffer having a data input connected to an output buffer data conductor, a data output connected to the I/O pad, and an enable input connected to an output buffer enable conductor; the input buffer data conductors extending in either the row or the column direction, different ones of the input buffer data conductors extending different numbers of rows or columns, the input buffer data conductors forming first intersections with inputs of the modules; the output buType: GrantFiled: May 18, 1995Date of Patent: April 29, 1997Assignee: Actel CorporationInventors: William C. Plants, Sinan Kaptanoglu, Jung-Cheun Lien, King W. Chan, Khaled A. El-Ayat
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Patent number: 5614818Abstract: A circuit for providing 100% observability and controllability of inputs and outputs of any function circuit module in an array of function circuit modules includes circuitry for placing a test data bit into a selected one of any of the function circuit modules, and circuitry for reading the output of a selected one of any of the function circuit modules.Type: GrantFiled: September 8, 1994Date of Patent: March 25, 1997Assignee: Actel CorporationInventors: Khaled El Ayat, King W. Chan, Theodore M. Speers
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Patent number: 5606267Abstract: A user-programmable gate array architecture includes an array of logic function modules which may comprise one or more combinatorial and/or sequential logic circuits. An interconnect architecture comprising a plurality of horizontal and vertical general interconnect channels, each including a plurality of interconnect conductors some of which may be segmented, is imposed on the array. Individual ones of the interconnect conductors are connectable to each other and to the inputs and outputs of the logic function modules by user-programmable interconnect elements. A local interconnect architecture comprising local interconnect channels is also imposed on the array. Each local interconnect channel includes a plurality of local interconnect conductors and runs between pairs of adjacent ones of the logic function modules.Type: GrantFiled: September 1, 1995Date of Patent: February 25, 1997Assignee: Actel CorporationInventors: Khaled A. El Ayat, Gregory W. Bakker, Jung-Cheun Lien, William C. Plants, Sinan Kaptanoglu, Runip Gopisetty, King W. Chan, Marko Chew
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Patent number: 5570041Abstract: A user-programmable gate array architecture includes an array of logic function modules which may comprise one or more combinatorial and/or sequential logic circuits. An interconnect architecture comprising a plurality of horizontal and vertical general interconnect channels, each including a plurality of interconnect conductors some of which may be segmented, is imposed on the array. Individual ones of the interconnect conductors are connectable to each other and to the inputs and outputs of the logic function modules by user-programmable interconnect elements. A local interconnect architecture comprising local interconnect channels is also imposed on the array. Each local interconnect channel includes a plurality of local interconnect conductors and runs between pairs of adjacent ones of the logic function modules.Type: GrantFiled: June 28, 1995Date of Patent: October 29, 1996Assignee: Actel CorporationInventors: Khaled A. El-Avat, Sinan Kaptanoglu, King W. Chan, William C. Plants, Jung-Cheun Lien