Abstract: A geometrical arithmetic unit obtains display coordinate data by coordinate transformation of drawing data, transfers the display coordinate data to the drawing unit when the drawing data is rotation target drawing data, and transfers the display coordinate data to a processor when the drawing data is non-rotation target drawing data. A processor controls transfer of an image of the non-rotation target drawing data to the drawing memory based on the display coordinate data. A drawing unit produces a rotated image based on the rotation target drawing data, and transfers the rotated image to the drawing memory based on the display coordinate data. Therefore, the processor and the drawing unit can perform the processing in parallel so that the drawing processing speed can be increased, and the drawing processing can be performed smoothly.

Abstract: In order to obtain a vertically enlarged image with no indentation, reset timing of a data skipping counter is changed between odd and even lines by one horizontal scanning line by an output of a selector. Thus, data skipping timing for a signal by an AND gate is displaced between odd and even frames by one horizontal scanning line, whereby positions of inserted lines overlappingly read from a display memory in correspondence to the skipping are also displaced between odd and even frames by one horizontal scanning line. Further, color data of the inserted lines are converted to those having low chromaticity levels by +1 processing by an adder, to be supplied to a display unit. Thus, indentation of an oblique thin line, for example, is blurred so that a smooth vertically enlarged image is obtained.

Abstract: A timing generator 12' applies a control signal SC1 consisting of a row address strobe signal RAS1, a column address strobe signal CAS1 and a writing control signal WE1 to a control input C of a DRAM 31 while it also applies a control signal SC2 consisting of a row address strobe signal RAS2, a column address strobe signal CAS2 and a writing control signal WE2 to a control input C of a DRAM 32. The control signals SC1and SC2 are produced in accordance with the least significant bit LSB of an inside address MA and independent of each other. The display data reading operation can be performed on each of memories (DRAMs) independent of each other, and therefore, the total period for the display data reading can be shortened, and accordingly, a saving of time allows an interruption of a longer period of the display data writing operation during the display period, and thus, a time for a display data renewal can be shortened.

Abstract: A gradation level selecting circuit for selecting a gradation level consists of first and second selecting circuits (28, 29) and a selector (30). The first selecting circuit selects one of gradation level signals from a gradation level generator in accordance with monochrome data from a monochrome data generator (24) and predetermined one of color data from a color data generator (23). The second selecting circuit selects one of the gradation level signals in accordance with the color data. The selector (30) selects an output of the first selecting circuit (28) or an output of the second selecting circuit (29) in response to a content of a switching resistor (25), to supply it to a monochrome display device. Thus, appropriate gradation display can be carried out by the monochrome display device using software either for color display or for monochrome display.