Abstract: Disclosed herein is a video signal processor including: a combining process section adapted to superimpose a first marker signal on a first video signal component at a specific position and superimpose a second marker signal on a second video signal component at roughly the same position as the specific position; and a control section adapted to control the condition of superimposition of the first and second marker signals so that an image appears to indicate that the first and second marker signals are combined correctly when the first and second video signal components are combined in a correct phase relationship, and so that an image appears to indicate that the first and second marker signals are combined incorrectly if the first and second video signal components are combined in an incorrect phase relationship.

Abstract: A transmission device includes: a transceiving unit transceiving a serial signal generated by serially converting data based on a clock signal of a frequency selected from frequencies used as clock components of the serial signal and including the clock signal of the selected frequency; a clock recovering unit receiving the serial signal received by the transceiving unit and recovers a recovered clock signal from the serial signal; a match determination unit receiving the recovered clock signal and determines whether a frequency of the recovered clock signal matches each of the frequencies; and a frequency controller performing, if the match determination unit determines that the frequency of the recovered clock signal matches each of the frequencies, a control to determine the frequency of the recovered clock signal as the matching frequency, wherein the frequency of the recovered clock signal is switched between the frequencies until the frequency is determined by the frequency controller.

Abstract: A transmission device includes: a transceiving unit transceiving a serial signal generated by serially converting data based on a clock signal of a frequency selected from frequencies used as clock components of the serial signal and including the clock signal of the selected frequency; a clock recovering unit receiving the serial signal received by the transceiving unit and recovers a recovered clock signal from the serial signal; a match determination unit receiving the recovered clock signal and determines whether a frequency of the recovered clock signal matches each of the frequencies; and a frequency controller performing, if the match determination unit determines that the frequency of the recovered clock signal matches each of the frequencies, a control to determine the frequency of the recovered clock signal as the matching frequency, wherein the frequency of the recovered clock signal is switched between the frequencies until the frequency is determined by the frequency controller.

Abstract: Disclosed herein is a video signal processor including: a combining process section adapted to superimpose a first marker signal on a first video signal component at a specific position and superimpose a second marker signal on a second video signal component at roughly the same position as the specific position; and a control section adapted to control the condition of superimposition of the first and second marker signals so that an image appears to indicate that the first and second marker signals are combined correctly when the first and second video signal components are combined in a correct phase relationship, and so that an image appears to indicate that the first and second marker signals are combined incorrectly if the first and second video signal components are combined in an incorrect phase relationship.