Abstract: An IC card system has, at least, an IC card having a first set of terminals and an external unit having a second set of terminals. The IC card has a detector for detecting a contact condition between the first and second sets of terminals, a controller, and an internal circuit such as an EEPROM. If the detector determines that the contact condition is faulty, the controller completes a given process, and then, stops the operation of the internal circuit. If an access operation to the internal circuit is in progress when the detector finds contact fault, the controller does not stop immediately and continues to complete the access operation, to prevent the writing or reading of erroneous data. The present invention also provides an IC card for the IC card system and a semiconductor IC incorporated in the IC card.

Abstract: An IC card has a peripheral circuit and a CPU. The peripheral circuit has a memory for storing data. The CPU controls various operations including an access operation of the memory. The IC card receives a supply voltage and a clock signal from an external unit. The IC card has a detector for detecting the supply voltage, a tester for testing the detected supply voltage, and an adjuster for adjusting the peripheral circuit according to a result of the voltage test. With these arrangements, the IC card stably operates on a wide range of supply voltages and is capable of coping with a fluctuation in the supply voltage. The tester may be incorporated in the CPU as one of functions thereof or may be realized by hardware that is arranged outside the CPU. The IC card and external unit constitute an IC card system.

Abstract: A storage section stores a plurality of programs. A central processing section controls execution of each of the plurality of programs stored in the storage section. A setting section, in cooperation with the central processing section, sets at least one of a disable area that inhibits accessing of another program and an enable area that allows accessing of another program, in each of the plurality of programs stored in the storage section.

Abstract: A memory data protection circuit is provided on a one-chip microcomputer having a CPU, ROM, volatile memory, and nonvolatile memory which together with an input/output control circuit are connected to each other via a first bus line. A security flag storage circuit receives a security flag consisting of a plurality of bits. In one state the security flag cannot be rewritten once it has been written. A security flag monitor circuit reads the security flag and when receiving the power-on reset signal recognizes the flag contents.

Abstract: A nonvolatile semiconductor memory device comprises an electrically erasable programmable memory cell array, a write-only word line and read-only word line provided in a row direction of the memory cell array and connected to corresponding memory cells and a write-only data line and read-only data line provided in a column direction of the memory cell array and connected to the memory cells.

Abstract: A display driving/controlling integrated circuit includes a display memory for storing data to be supplied to a display unit, a bus line of n-bit configuration for transmitting display data to be stored in the display memory, with n bits set as one unit, and a data array direction selection circuit connected to the bus line, for outputting display data on the bus line to the display memory with the bit array thereof kept in the original bit array status or outputting the display data to the display memory with the bit array thereof inverted with respect to the original bit array. There is provided means for writing display data with the bit array thereof inverted with respect to the original bit array when the display data is written into the display memory.