Abstract: A method of sidewall engineering with negative capacitance materials is disclosed. For example, the negative capacitance material is a ferroelectric material. The method includes providing a dielectric liner on the sidewall of the gate and providing a negative capacitance liner or spacer over the dielectric liner. In one embodiment, the dielectric liner is an oxide liner and the negative capacitance liner or spacer is a ferroelectric liner or spacer. The engineered negative capacitance liner or spacer enhances the gate-to-S/D region and gate-to-contact coupling and hence the device ION-IOFF performance is improved.

Abstract: Integrated circuits including tunnel transistors and methods for fabricating such integrated circuits are provided. An exemplary method for fabricating an integrated device includes forming a lower source/drain region in and/or over a semiconductor substrate. The method forms a channel region overlying the lower source/drain region. The method also forms an upper source/drain region overlying the channel region. The method includes forming a gate structure beside the channel region.

Abstract: A device and a method for forming a device are disclosed. The method includes providing a substrate prepared with a device region. A device well having second polarity type dopants is formed in the substrate. A threshold voltage (VT) implant is performed with a desired level of second polarity type dopants into the substrate. The VT implant forms a VT adjust region to obtain a desired VT of a transistor. A co-implantation with diffusion suppression material is performed to form a diffusion suppression (DS) region in the substrate. The DS region reduces or prevents segregation and out-diffusion of the VT implanted second polarity type dopants. A transistor of a first polarity type having a gate is formed in the device region. First and second diffusion regions are formed adjacent to sidewalls of the gate.

Abstract: A non-volatile memory (NVM) device and a method for forming the NVM device are presented. The NVM device includes a substrate having a device region, a gate stack having a floating gate (FG) and a control gate (CG) over the device region, and source/drain (S/D) regions adjacent to the sidewalls of the gate. The FG includes a FG dielectric and a FG electrode. The CG includes a composite CG dielectric and a CG electrode. The composite CG dielectric includes a first CG dielectric and a ferroelectric second CG dielectric. The ferroelectric second CG dielectric is configured to have a negative capacitance to increase gate coupling ratio of the NVM device.

Abstract: Memory cells and methods for forming a memory cell are disclosed. The memory cell includes a first selector having a first gate coupled to a first word line (WL) and first and second source/drain (S/D) regions, and a second selector having a second gate coupled to a second WL and first and second S/D regions. The second S/D regions of the first and the second selectors are a common S/D region. The first and the second WLs are a common WL and the second S/D regions of the first and second selectors are coupled to a source line (SL). The memory cell includes a storage element which includes a magnetic tunnel junction (MTJ) element coupled with a bit line (BL) and the first and the second selectors, and a voltage control switch which includes a metal-insulator-transition (MIT) material coupled with the first selector.

Abstract: A device and methods for forming the device are disclosed. The method includes providing a substrate prepared with a memory cell region and forming memory cell pairs in the cell region. The memory cell pair comprises of first and second split gate memory cells. Each memory cell includes a first gate serving as an access gate, a second gate adjacent to the first gate, the second gate serving as a storage gate, a first source/drain (S/D) region adjacent to the first gate and a second S/D region adjacent to the second gate. The method also includes forming silicide contacts on the substrate on the gate conductors and first S/D regions and exposed buried common source lines (SLs) in pick-up regions, such that increasing the displacement distance in the wordline and source line (WLSL) region to an extended displacement distance DE avoids shorting between the first offset access gate conductors and adjacent access gate conductors of the rows of memory cell pairs.

Abstract: Embodiments of a multi-time programmable (MTP) structure for non-volatile memory cells are presented. The memory cell includes an ultra-thin silicon-on-insulator (SOI) substrate. A transistor having a floating gate is disposed on the SOI substrate. The transistor comprises first and second source/drain (S/D) regions disposed adjacent to sides of the floating gate. A control capacitor having a control gate is disposed on the SOI substrate. The control gate is directly coupled to the floating gate. A device well is disposed in the base substrate and underlaps the floating gate and the control gate. A capacitor back-gate is embedded within the base substrate and in electrical communication with the control gate. A contact region is disposed within the device well.

Abstract: Embodiments of a multi-time programmable (MTP) structure for non-volatile memory cells are presented. The memory cell includes an ultra-thin silicon-on-insulator (SOI) substrate. A transistor having a floating gate is disposed on the SOI substrate. The transistor comprises first and second source/drain (S/D) regions disposed adjacent to sides of the floating gate. A control capacitor having a control gate is disposed on the SOI substrate. The control gate is directly coupled to the floating gate. A device well is disposed in the base substrate and underlaps the floating gate and the control gate. A capacitor back-gate is embedded within the base substrate and in electrical communication with the control gate. A contact region is disposed within the device well.

Abstract: A device and methods for forming the device are disclosed. The method includes providing a substrate prepared with a memory cell region and forming memory cell pairs in the cell region. The memory cell pair comprises of first and second split gate memory cells. Each memory cell includes a first gate serving as an access gate, a second gate adjacent to the first gate, the second gate serving as a storage gate, a first source/drain (S/D) region adjacent to the first gate and a second S/D region adjacent to the second gate. The method also includes forming silicide contacts on the substrate on the gate conductors and first S/D regions and exposed buried common source lines (SLs) in pick-up regions, such that increasing the displacement distance in the wordline and source line (WLSL) region to an extended displacement distance DE avoids shorting between the first offset access gate conductors and adjacent access gate conductors of the rows of memory cell pairs.

Abstract: Integrated circuits and methods of producing the same are provided. In an exemplary embodiment, an integrated circuit includes a first capacitor with a first gate overlying a first gate dielectric that in turn overlies a first channel. a second capacitor includes a second gate overlying a second gate dielectric that in turn overlies a second channel. The second gate dielectric has a different composition than the first gate dielectric. A capacitor interconnect is in electrical communication with the first capacitor and with the second capacitor.

Abstract: Integrated circuits and methods of producing the same are provided. In an exemplary embodiment, an integrated circuit includes a substrate with an active layer overlying a buried insulator layer that in turn overlies a handle layer, where the active layer includes a first active well. A first source, a first drain, and a first channel are defined within the first active well, where the first channel is between the first source and the first drain. A first gate dielectric directly overlies the first channel, and a first gate directly overlies the first gate dielectric, where a first capacitor includes the first source, the first drain, the first channel, the first gate dielectric, and the first gate. A first handle well is defined within the handle layer directly underlying the first channel and the buried insulator layer.

Abstract: Multi-time programmable (MTP) memory cells, integrated circuits including MTP memory cells, and methods for fabricating MTP memory cells are provided. In an embodiment, an MTP memory cell includes a semiconductor substrate including a CMOS device region and a DMOS device region. The MTP memory cell further includes a high voltage (HV) p-well in the CMOS device region and in the DMOS device region of the semiconductor substrate. An n-channel transistor is disposed over the HV p-well in the CMOS device region and includes a transistor gate. Also, the MTP memory cell includes an n-well overlying the HV p-well in the DMOS region of the semiconductor substrate. An n-channel capacitor is disposed over the n-well and includes a capacitor gate. The capacitor gate is coupled to the transistor gate.

Abstract: Integrated circuits, nonvolatile memory (NVM) structures, and methods for fabricating integrated circuits with NVM structures are provided. An exemplary integrated circuit includes a substrate and a dual-bit NVM structure overlying the substrate. The dual-bit NVM structure includes primary, first adjacent and second adjacent fin structures laterally extending in parallel over the substrate. The primary fin structure includes source, channel and drain regions. Each adjacent fin structure includes a program/erase gate. The dual-bit NVM structure further includes a first floating gate located between the channel region of the primary fin structure and the first adjacent fin structure and a second floating gate located between the channel region of the primary fin structure and the second adjacent fin structure. Also, the dual-bit NVM structure includes a control gate adjacent the primary fin structure.

Abstract: Memory cells and methods of forming memory cells are disclosed. The memory cell includes a substrate and a select transistor. The select transistor includes a gate disposed over the substrate between first and second source/drain (S/D) terminals. The first and second S/D terminals are configured such that a resistance at the second S/D terminal is higher than a resistance at the first S/D terminal. A dielectric layer disposed over the substrate includes a plurality of inter level dielectric (ILD) layers. A lower portion of the dielectric layer includes a first contact level and a first metal level. A first contact plug disposed within the first contact level connects the first S/D terminal to a first metal line in the first metal level. A magnetic tunnel junction (MTJ) element is disposed directly on and in contact with a top of the first metal line.

Abstract: Devices and methods of forming a device are disclosed. The method includes providing a substrate with a cell region. Selector units and storage units are formed within the substrate. The selector unit includes first and second bipolar junction transistors (BJTs). The selector unit includes first and second bipolar junction transistors (BJTs). A BJT includes first, second and third BJT terminals. The second BJT terminals of the first and second BJTs are coupled to or serve as a common wordline terminal. The third BJT terminal of the first BJT serves as a first bitline terminal, and the third BJT terminal of the second BJT serves as a second bitline terminal. A storage unit is disposed over the selector unit.

Abstract: A gate-grounded metal oxide semiconductor (GGMOS) device is disclosed. The GGMOS is an n-type (GGNMOS) transistor used as an electrostatic discharge (ESD) protection device. The GGMOS includes a base extension region under an elevated source. The elevated source and base extension regions increase Leff and reduce beta, increasing performance of the ESD protection.

Abstract: Integrated circuits, nonvolatile memory (NVM) structures, and methods for fabricating integrated circuits with NVM structures are provided. An exemplary integrated circuit includes a substrate and a dual-bit NVM structure overlying the substrate. The dual-bit NVM structure includes primary, first adjacent and second adjacent fin structures laterally extending in parallel over the substrate. The primary fin structure includes source, channel and drain regions. Each adjacent fin structure includes a program/erase gate. The dual-bit NVM structure further includes a first floating gate located between the channel region of the primary fin structure and the first adjacent fin structure and a second floating gate located between the channel region of the primary fin structure and the second adjacent fin structure. Also, the dual-bit NVM structure includes a control gate adjacent the primary fin structure.

Abstract: Integrated circuits and methods of producing the same are provided. In an exemplary embodiment, an integrated circuit includes a first capacitor with a first gate overlying a first gate dielectric that in turn overlies a first channel. a second capacitor includes a second gate overlying a second gate dielectric that in turn overlies a second channel. The second gate dielectric has a different composition than the first gate dielectric. A capacitor interconnect is in electrical communication with the first capacitor and with the second capacitor.

Abstract: Integrated circuits and methods of producing the same are provided. In an exemplary embodiment, an integrated circuit includes a substrate with an active layer overlying a buried insulator layer that in turn overlies a handle layer, where the active layer includes a first active well. A first source, a first drain, and a first channel are defined within the first active well, where the first channel is between the first source and the first drain. A first gate dielectric directly overlies the first channel, and a first gate directly overlies the first gate dielectric, where a first capacitor includes the first source, the first drain, the first channel, the first gate dielectric, and the first gate. A first handle well is defined within the handle layer directly underlying the first channel and the buried insulator layer.

Abstract: Devices and methods for forming a device are presented. The method includes providing a substrate prepared with at least a first region for accommodating an anti-fuse based memory cell. A fin structure is formed in the first region. The fin structure includes top and bottom fin portions and includes channel and non-channel regions defined along the length of the fin structure. An isolation layer is formed on the substrate. The isolation layer has a top isolation surface disposed below a top fin surface, leaving the top fin portion exposed. At least a portion of the exposed top fin portion in the channel region is processed to form a sharpened tip profile at top of the fin. A gate having a gate dielectric and a metal gate electrode is formed over the substrate. The gate wraps around the channel region of the fin structure.