Patents by Inventor Kiran Devanahalli

Kiran Devanahalli has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7676000
    Abstract: A technique for signal distortion compensation using a filter that can support a higher delay spread distortion without substantially increasing hardware complexity. In one example embodiment, an adaptive receiver design compensates for signal distortions with the use of non-uniform tap delay filters. The non-uniform tap delay filters are used to output an adaptively channel matched signal for decoding.
    Type: Grant
    Filed: January 15, 2004
    Date of Patent: March 9, 2010
    Assignee: Ittiam Systems (P) Ltd.
    Inventors: Rahul Garg, Shobha Ramaswamy, Kiran Devanahalli, Satyanarayana Sanpini
  • Patent number: 7463681
    Abstract: A decision feedback equalizer (DFE) has an inter symbol interference (ISI) loop and inter chip interference (ICI) loop. A buffer at the input of the DFE loop receives a (CCK based data rate) signal coming into the DFE, retains a predetermined number of chips from each incoming symbol and assists to meet timing requirements by chip management. An outgoing rate for the chips from the buffer may depend on the incoming rate and may be higher than the incoming rate by a known factor. A method of designing a configuration for the DFE takes into consideration the timing delay in the loops. The operation within the DFE loop is pipelined, and any latency due to the pipelining is handled at a CCK demodulator. A method for designing the DFE architecture and an article comprising a storage medium with instructions thereon for executing the method, are also disclosed.
    Type: Grant
    Filed: May 4, 2005
    Date of Patent: December 9, 2008
    Assignee: Ittiam Systems (P) Ltd.
    Inventors: Rahul Garg, Kiran Devanahalli, Aparna Chakrakodi Krishnashastry
  • Publication number: 20050254572
    Abstract: A decision feedback equalizer (DFE) has an inter symbol interference (ISI) loop and inter chip interference (ICI) loop. A buffer at the input of the DFE loop receives a (CCK based data rate) signal coming into the DFE, retains a predetermined number of chips from each incoming symbol and assists to meet timing requirements by chip management. An outgoing rate for the chips from the buffer may depend on the incoming rate and may be higher than the incoming rate by a known factor. A method of designing a configuration for the DFE takes into consideration the timing delay in the loops. The operation within the DFE loop is pipelined, and any latency due to the pipelining is handled at a CCK demodulator. A method for designing the DFE architecture and an article comprising a storage medium with instructions thereon for executing the method, are also disclosed.
    Type: Application
    Filed: May 4, 2005
    Publication date: November 17, 2005
    Inventors: Rahul Garg, Kiran Devanahalli, Aparna Krishnashastry
  • Publication number: 20050159120
    Abstract: A technique for signal distortion compensation using a filter that can support a higher delay spread distortion without substantially increasing hardware complexity. In one example embodiment, an adaptive receiver design compensates for signal distortions with the use of non-uniform tap delay filters. The non-uniform tap delay filters are used to output an adaptively channel matched signal for decoding.
    Type: Application
    Filed: January 15, 2004
    Publication date: July 21, 2005
    Inventors: Rahul Garg, Shobha Ramaswamy, Kiran Devanahalli, Satyanarayana Sanpini