Patents by Inventor Kiran Pangal
Kiran Pangal has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11705197Abstract: Methods, systems, and devices for a modified write voltage for memory devices are described. In an example, the memory device may determine a first set of memory cells to be switched from a first logic state (e.g., a SET state) to a second logic state (e.g., a RESET state) based on a received write command. The memory device may perform a read operation to determine a subset of the first set of memory cells (e.g., a second set of memory cells) having a conductance threshold satisfying a criteria based on a predicted drift of the memory cells. The memory device may apply a RESET pulse to each of the memory cells within the first set of memory cells, where the RESET pulse applied to the second set of memory cells is modified to decrease voltage threshold drift in the RESET state.Type: GrantFiled: October 14, 2021Date of Patent: July 18, 2023Assignee: Micron Technology, Inc.Inventors: Sandeepan Dasgupta, Sanjay Rangan, Koushik Banerjee, Nevil Gajera, Mase J. Taub, Kiran Pangal
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Publication number: 20230064007Abstract: In one embodiment, a state is encoded into a memory cell comprising a phase change material (PM) region and a select device (SD) region by: applying a first current in the memory cell over a first time period, wherein the first current applied over the first time period causes the PM region of the memory cell to be placed into an amorphous state and the SD region of the memory cell to be placed into an amorphous state; and applying a second current in the memory cell over a second time period after the first time period, wherein the second current applied over the third time period causes the SD region of the memory cell to be placed into a crystalline state and the PM region of the memory cell to remain in the amorphous state.Type: ApplicationFiled: August 20, 2021Publication date: March 2, 2023Applicant: Intel CorporationInventors: Rouhollah Mousavi Iraei, Kiran Pangal, Saad P. Monasa, Mini Goel, Raymond Zeng, Hemant P. Rao
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Publication number: 20220415425Abstract: A read technique for both SLC (single level cell) and MLC (multi-level cell) cross-point memory can mitigate drift-related errors with minimal or no drift tracking. In one example, a read at a higher magnitude voltage is applied first, which causes the drift for cells in a lower threshold voltage state to be reset. In one example, the read at the first voltage can be a full float read to minimize disturb. A second read can then be performed at a lower voltage without the need to adjust the read voltage due to drift.Type: ApplicationFiled: June 25, 2021Publication date: December 29, 2022Inventors: Hemant P. RAO, Raymond W. ZENG, Prashant S. DAMLE, Zion S. KWOK, Kiran PANGAL, Mase J. TAUB
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Patent number: 11322546Abstract: A single memory cell array is formed to maintain current delivery and mitigate current spike through the deposition of resistive materials in two or more regions of the array, including at least one region of memory cells nearer to contacts on the conductive lines and at least one region of memory cells farther from the contacts, where the contacts connect the conductive lines to the current source. Higher and lower resistive materials are introduced during the formation of the memory cells and the conductive lines based on the boundaries and dimensions of the two or more regions using a photo mask. Multiple memory cell arrays formed to maintain current delivery and mitigate current spike can be arranged into a three-dimensional memory cell array. The regions of memory cells in each memory cell array can vary depending on resistance at the contacts on the conductive lines that provide access to the memory cells, where the resistance can vary from one memory cell array to another.Type: GrantFiled: September 27, 2018Date of Patent: May 3, 2022Assignee: Intel CorporationInventors: Shafqat Ahmed, Kiran Pangal
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Publication number: 20220068385Abstract: Methods, systems, and devices for a modified write voltage for memory devices are described. In an example, the memory device may determine a first set of memory cells to be switched from a first logic state (e.g., a SET state) to a second logic state (e.g., a RESET state) based on a received write command. The memory device may perform a read operation to determine a subset of the first set of memory cells (e.g., a second set of memory cells) having a conductance threshold satisfying a criteria based on a predicted drift of the memory cells. The memory device may apply a RESET pulse to each of the memory cells within the first set of memory cells, where the RESET pulse applied to the second set of memory cells is modified to decrease voltage threshold drift in the RESET state.Type: ApplicationFiled: October 14, 2021Publication date: March 3, 2022Inventors: Sandeepan Dasgupta, Sanjay Rangan, Koushik Banerjee, Nevil Gajera, Mase J. Taub, Kiran Pangal
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Patent number: 11170853Abstract: Methods, systems, and devices for a modified write voltage for memory devices are described. In an example, the memory device may determine a first set of memory cells to be switched from a first logic state (e.g., a SET state) to a second logic state (e.g., a RESET state) based on a received write command. The memory device may perform a read operation to determine a subset of the first set of memory cells (e.g., a second set of memory cells) having a conductance threshold satisfying a criteria based on a predicted drift of the memory cells. The memory device may apply a RESET pulse to each of the memory cells within the first set of memory cells, where the RESET pulse applied to the second set of memory cells is modified to decrease voltage threshold drift in the RESET state.Type: GrantFiled: March 4, 2020Date of Patent: November 9, 2021Assignee: Micron Technology, Inc.Inventors: Sandeepan Dasgupta, Sanjay Rangan, Koushik Banerjee, Nevil Gajera, Mase J. Taub, Kiran Pangal
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Patent number: 11145366Abstract: Examples may include techniques to mitigate errors during a read operation to a memory cell of a memory array. Examples include selecting the memory cell and applying one of multiple demarcation read voltages for respective multiple time intervals to sense a state of a resistive storage element of the memory cell. Examples also include applying a bias voltage to the memory cell following a sense interval to mitigate read disturb to the resistive storage element incurred while the one of the multiple demarcation read voltages was applied to the memory cell.Type: GrantFiled: March 24, 2020Date of Patent: October 12, 2021Assignee: Intel CorporationInventors: Davide Mantegazza, Kiran Pangal
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Publication number: 20210304817Abstract: Examples may include techniques to mitigate errors during a read operation to a memory cell of a memory array. Examples include selecting the memory cell and applying one of multiple demarcation read voltages for respective multiple time intervals to sense a state of a resistive storage element of the memory cell. Examples also include applying a bias voltage to the memory cell following a sense interval to mitigate read disturb to the resistive storage element incurred while the one of the multiple demarcation read voltages was applied to the memory cell.Type: ApplicationFiled: March 24, 2020Publication date: September 30, 2021Inventors: Davide MANTEGAZZA, Kiran PANGAL
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Publication number: 20210280244Abstract: Methods, systems, and devices for a modified write voltage for memory devices are described. In an example, the memory device may determine a first set of memory cells to be switched from a first logic state (e.g., a SET state) to a second logic state (e.g., a RESET state) based on a received write command. The memory device may perform a read operation to determine a subset of the first set of memory cells (e.g., a second set of memory cells) having a conductance threshold satisfying a criteria based on a predicted drift of the memory cells. The memory device may apply a RESET pulse to each of the memory cells within the first set of memory cells, where the RESET pulse applied to the second set of memory cells is modified to decrease voltage threshold drift in the RESET state.Type: ApplicationFiled: March 4, 2020Publication date: September 9, 2021Inventors: Sandeepan Dasgupta, Sanjay Rangan, Koushik Banerjee, Nevil Gajera, Mase J. Taub, Kiran Pangal
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Patent number: 11107523Abstract: Multi-level cell (MLC) cross-point memory cells can store more than 1 bit per cell. In one example, MLC write operations for cross-point memory can be achieved by independently changing the state of the switch element and the memory element. The memory cell can be programmed to multiple states, such as a high threshold voltage state (where both the memory element and switch element exhibit a high threshold voltage or resistance), a low threshold voltage state (where both the memory element and select element exhibit a low threshold voltage or resistance), and one or more intermediate resistance states. In one example, additional resistance states can be programmed by setting the switch element and memory element to opposite states (e.g., one of the switch element and memory element is in a high resistance state and the other is in a low resistance state) or by placing both the switch element and memory element in different intermediate states.Type: GrantFiled: March 24, 2020Date of Patent: August 31, 2021Assignee: Intel CorporationInventors: Sanjay Rangan, Kiran Pangal
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Patent number: 11024380Abstract: Nonvolatile memory (e.g. phase change memory) devices, systems, and methods that minimize energy expenditure and wear while providing greatly improved error rate with respect to marginal bits are disclosed and described.Type: GrantFiled: November 15, 2019Date of Patent: June 1, 2021Assignee: Intel CorporationInventors: Daniel Chu, Kiran Pangal, Mase Taub, Sandeep Guliani, Raymond Zeng
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Patent number: 10957387Abstract: Techniques for accessing multi-level cell (MLC) crosspoint memory cells are described. In one example, a circuit includes a crosspoint memory cell that can be in one of multiple resistive states (e.g., four or more resistive states). In one example, to perform a read, circuitry coupled with the memory cell applies one or more sub-reads at different read voltages. For example, the circuitry applies a first read voltage and detects if the memory cell thresholds in response to the first read voltage. If the memory cell thresholded in response to the first read voltage, the state of the memory cell can be determined without further reads. If the memory cell did not threshold in response to the first read voltage, a second read voltage with a greater magnitude is applied across the memory cell. If the memory cell thresholded in response to the second read voltage, the state of the memory cell can be determined without further reads.Type: GrantFiled: November 18, 2019Date of Patent: March 23, 2021Assignee: Intel CorporationInventors: Davide Mantegazza, Kiran Pangal, Sanjay Rangan
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Patent number: 10936418Abstract: Uncorrectable memory errors may be reduced by determining a logical array address for a set of memory arrays and transforming the logical array address to at least two unique array addresses based, at least in part, on logical locations of at least two memory arrays within the set of memory arrays. The at least two memory arrays are then accessed using the at least two unique array addresses, respectively.Type: GrantFiled: June 18, 2019Date of Patent: March 2, 2021Assignee: Intel CorporationInventors: Kiran Pangal, Prashant S. Damle, Rajesh Sundaram, Shekoufeh Qawami, Julie M. Walker, Doyle Rivers
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Patent number: 10902911Abstract: Threshold switching devices demonstrating transient current protection through both insulation and repair current mechanisms, including associated systems and methods, are provided and discussed.Type: GrantFiled: November 6, 2019Date of Patent: January 26, 2021Assignee: Intel CorporationInventors: Davide Mantegazza, Sandeep Guliani, Balaji Srinivasan, Kiran Pangal
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Patent number: 10783966Abstract: Phase change material can be set with a multistage set process. Set control logic can heat a phase change semiconductor material (PM) to a first temperature for a first period of time. The first temperature is configured to promote nucleation of a crystalline state of the PM. The control logic can increase the temperature to a second temperature for a second period of time. The second temperature is configured to promote crystal growth within the PM. The nucleation and growth of the crystal set the PM to the crystalline state. The multistage ramping up of the temperature can improve the efficiency of the set process relative to traditional approaches.Type: GrantFiled: October 4, 2019Date of Patent: September 22, 2020Assignee: Intel CorporationInventors: Sanjay Rangan, Kiran Pangal, Nevil N Gajera, Lu Liu, Gayathri Rao Subbu
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Publication number: 20200160908Abstract: Nonvolatile memory (e.g. phase change memory) devices, systems, and methods that minimize energy expenditure and wear while providing greatly improved error rate with respect to marginal bits are disclosed and described.Type: ApplicationFiled: November 15, 2019Publication date: May 21, 2020Inventors: Daniel Chu, Kiran Pangal, Mase Taub, Sandeep Guliani, Raymond Zeng
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Publication number: 20200143881Abstract: Threshold switching devices demonstrating transient current protection through both insulation and repair current mechanisms, including associated systems and methods, are provided and discussed.Type: ApplicationFiled: November 6, 2019Publication date: May 7, 2020Applicant: Intel CorporationInventors: Davide Mantegazza, Sandeep Guliani, Balaji Srinivasan, Kiran Pangal
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Publication number: 20200035300Abstract: Phase change material can be set with a multistage set process. Set control logic can heat a phase change semiconductor material (PM) to a first temperature for a first period of time. The first temperature is configured to promote nucleation of a crystalline state of the PM. The control logic can increase the temperature to a second temperature for a second period of time. The second temperature is configured to promote crystal growth within the PM. The nucleation and growth of the crystal set the PM to the crystalline state. The multistage ramping up of the temperature can improve the efficiency of the set process relative to traditional approaches.Type: ApplicationFiled: October 4, 2019Publication date: January 30, 2020Inventors: Sanjay RANGAN, Kiran PANGAL, Nevil N. GAJERA, Lu LIU, Gayathri RAO SUBBU
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Patent number: 10546634Abstract: The present disclosure relates to phase change memory control. An apparatus includes a memory controller. The memory controller includes a word line (WL) control module and a bit line (BL) control module. The memory controller is to determine a WL address based, at least in part, on a received memory address. The memory controller is further to determine a BL address. The apparatus further includes a parameter selection module to select a value of a control parameter based, at least in part, on at least one of the WL address and/or the BL address.Type: GrantFiled: September 24, 2018Date of Patent: January 28, 2020Assignee: Intel CorporationInventors: Raymond W. Zeng, Mase J. Taub, Kiran Pangal, Sandeep K. Guliani
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Publication number: 20190370112Abstract: Uncorrectable memory errors may be reduced by determining a logical array address for a set of memory arrays and transforming the logical array address to at least two unique array addresses based, at least in part, on logical locations of at least two memory arrays within the set of memory arrays. The at least two memory arrays are then accessed using the at least two unique array addresses, respectively.Type: ApplicationFiled: June 18, 2019Publication date: December 5, 2019Inventors: Kiran PANGAL, Prashant S. DAMLE, Rajesh SUNDARAM, Shekoufeh QAWAMI, Julie M. WALKER, Doyle RIVERS