Patents by Inventor Kiran S. Panesar

Kiran S. Panesar has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7685401
    Abstract: Embodiments of apparatuses, methods, and systems for guest to host address translations for devices to access memory in a partitioned system are disclosed. In one embodiment, an apparatus includes an interface, partitioning logic, first address translation logic, and second address translation logic. The interface is to receive a request from a device to access memory in a partitioned system. The partitioning logic is to determine whether the device is assigned to a first partition or a second partition. The first address translation logic is to translate a first guest address to a first host address in the first partition. The second address translation logic is to translate a second guest address to a second host address in the second partition.
    Type: Grant
    Filed: December 27, 2006
    Date of Patent: March 23, 2010
    Assignee: Intel Corporation
    Inventors: Suresh Sugumar, Kiran S. Panesar, Narayan N. Iyer
  • Patent number: 7644407
    Abstract: A method, apparatus and system are described for seamlessly and concurrently sharing a graphics device amongst multiple virtual machines (“VMs”) on a host computer. Specifically, according to one embodiment of the invention, a graphics device may be shared by multiple VMs such that only the output of one VM (i.e., the “focus VM”) is displayed on a display device coupled to the host computer. The focus VM may be identified according to a variety of ways. The focus VM may render its output into a frame-buffer and/or an overlay buffer, and the page table entries (“PTEs) that point to the frame-buffer may then be copied to a display buffer in an unused memory location associated with the focus VM. The PTEs may additionally be copied to display buffers in unused memory locations associated with the non-focus VMs on the host. The display buffer may then output its display (via the pointers to the frame buffers) to the display device.
    Type: Grant
    Filed: March 5, 2004
    Date of Patent: January 5, 2010
    Assignee: Intel Corporation
    Inventors: David J. Cowperthwaite, Michael A. Goldsmith, Kiran S. Panesar
  • Publication number: 20090144531
    Abstract: A method of booting up a computer system comprising a first multi-cored processor comprising a first plurality of cores and a second multi-cored processor comprising a second plurality of cores is disclosed. The method may comprise configuring a first partition comprising a first one or more cores from the first plurality of cores and from the second plurality of cores, configuring a second partition comprising a second one or more cores from the first plurality of cores and from the second plurality of cores, and configuring a third partition comprising a third one or more cores from the first plurality of cores and one or more cores from the second plurality of cores.
    Type: Application
    Filed: November 30, 2007
    Publication date: June 4, 2009
    Inventors: Ajay Harikumar, Tessil Thomas, Biju P. Simon, Kiran S. Panesar
  • Patent number: 7454756
    Abstract: A method, apparatus and system are described for seamlessly sharing I/O devices amongst multiple virtual machines (“VMs”) on a host computer. Specifically, according to one embodiment of the invention, the virtual machine manager (“VMM”) on the host cycles access to the I/O devices amongst the VMs according to a round robin or other such allocation scheme. In order to provide direct access to the devices, the VMM may save the device state pertaining to the currently active VM, store the state in a memory region allocated to the currently active VM, retrieve a device state for a new VM from its memory region and restore the device using the retrieved device state, thus providing the illusion that each VM has direct, full-speed, exclusive access to the I/O device.
    Type: Grant
    Filed: March 5, 2004
    Date of Patent: November 18, 2008
    Assignee: Intel Corporation
    Inventors: Philip R. Lantz, Michael A. Goldsmith, David J. Cowperthwaite, Kiran S. Panesar
  • Publication number: 20080222338
    Abstract: A method and apparatus for sharing peripheral devices between multiple execution domains of a hardware platform are described. In one embodiment, the method includes the configuration end-point devices, bridges and interconnects of a hardware platform including at least two execution domains. When a configuration requests is issued from an execution domain, the configuration requests may be intercepted. Hence, the received configuration request is not used to configure the peripheral end-points, bridges or interconnects of the hardware platform. Configuration information decoded from intercepted configuration request may be stored as virtual configuration information. In one embodiment, configuration information is read from a target of the configuration request to identify actual configuration information.
    Type: Application
    Filed: March 7, 2007
    Publication date: September 11, 2008
    Inventors: Ramasubramanian Balasubramanian, Kiran S. Panesar
  • Publication number: 20080162864
    Abstract: Embodiments of apparatuses, methods, and systems for guest to host address translations for devices to access memory in a partitioned system are disclosed. In one embodiment, an apparatus includes an interface, partitioning logic, first address translation logic, and second address translation logic. The interface is to receive a request from a device to access memory in a partitioned system. The partitioning logic is to determine whether the device is assigned to a first partition or a second partition. The first address translation logic is to translate a first guest address to a first host address in the first partition. The second address translation logic is to translate a second guest address to a second host address in the second partition.
    Type: Application
    Filed: December 27, 2006
    Publication date: July 3, 2008
    Inventors: Suresh Sugumar, Kiran S. Panesar, Narayan N. Iyer
  • Publication number: 20080162865
    Abstract: Embodiments of apparatuses, methods, and systems for partitioning memory mapped device configuration space are disclosed. In one embodiment, an apparatus includes a configuration space address storage location, an access map storage location, and addressing logic. The configuration space address storage location is to store a pointer to a memory region to which transactions to configure devices in a partition of a partitioned system are addressed. The access map storage location is to store an access map or a pointer to an access map. The addressing logic is to use the access map to determine whether a configuration transaction from a processor to one of the devices is to be allowed.
    Type: Application
    Filed: December 29, 2006
    Publication date: July 3, 2008
    Inventors: David A. Koufaty, John I. Garney, Ulhas Warrier, Kiran S. Panesar
  • Publication number: 20080005500
    Abstract: A method, apparatus, and system, the method including, in some embodiments, updating a data structure of a second processor with an internal resource base address register (BAR) of a first processor, requesting access to the internal resource of the first processor by the second processor based on the updated data structure of the second processor, and providing, in response to the request of the second processor, access to the internal resource of the first processor to the second processor.
    Type: Application
    Filed: June 28, 2006
    Publication date: January 3, 2008
    Inventors: Mansoor Ahamed Basheer Ahamed, Kiran S. Panesar, Padmashree K. Apparao