Abstract: A method of forming silicide is described. A layer of refractory metal is deposited on a substrate, and then a first annealing process is performed to form silicide, followed by removal of unreacted metal. Next, a species implanting process is carried out to implant species of neutral atoms into the silicide to break up lattice structure of the silicide, so that the problem of junction leakage induced by spiking and piping diffusion under high temperature during a subsequent second annealing process is avoided.

Abstract: The proposed invention is related to a method for forming a gate with metal silicide. In short, the proposed method comprises the following steps: providing a substrate; forming a first dielectric layer on the substrate; forming a polysilicon layer on the first dielectric layer; forming a metal silicide layer on the polysilicon layer; forming a second dielectric layer on the metal silicide layer; etching the second dielectric layer, the metal silicide layer, the polysilicon layer and the first dielectric layer to form a gate; performing a thermal nitridation process to form a metal nitride layer on the sidewall of the metal silicide layer; and performing a thermal oxidation process to eliminate edge defects.

Abstract: A method for preventing polycide gate spiking, which essentially comprises the following steps: forms an oxide layer on a substrate; forming a polysilicon layer on the oxide layer; sputtering a barrier layer on the polysilicon layer; performing a first rapid thermal process; sputtering a silicide layer on the barrier layer; performing a photolithography process and an etching process to remove part of the silicide layer, part of the barrier layer and part of the polysilicon layer to form a polycide gate; and performing a second rapid thermal process. Further, as it is necessary to use both rapid thermal processes, the invention can be expanded such that only one rapid thermal process is applied. Both rapid thermal processes use almost no oxygen.

Abstract: A method for preventing polycide gate spiking, which essentially comprises following steps: forms an oxide layer on a substrate; forms a polysilicon layer on the oxide layer; sputters a barrier layer on the polysilicon layer; performs a first rapid thermal process; sputters a silicide layer on the barrier layer; performs a photolithography process and an etching process to remove part of the silicide layer, part of the barrier layer and part of the polysilicon layer to form a polycide gate; and performs a second rapid thermal process. Further, it is necessary to use both rapid thermal processes, the invention can be expand to only one rapid thermal process is applied. Beside, both rapid thermal processes almost don't use oxygen.

Abstract: A method of fabricating a self-aligned contact (SAC) and gate structure is described. A gate oxide layer, a conductive gate a cap layer and a source/drain are formed on a substrate. A conformal buffer layer is formed. An undoped polysilicon spacer is formed. A dielectric layer is formed over the substrate. Photolithography and etching technologies are used to form a self-aligned opening in the dielectric layer and conformal buffer layer. The self-aligned contact opening is filled with a conductive layer, to form a self-aligned contact.

Abstract: A method for forming a transistor in integrated circuits is disclosed. The method includes the following steps. A substrate is first provided. An insulating layer is then formed on the substrate. A conductor layer is formed on the insulating layer. Subsequently, a patterned photoresist layer is formed on the conductor layer. Next, an etch process is used to etch the conductor layer which has a sidewall. The patterned photoresist layer is then removed. After forming a liner layer on the sidewall of the conductor layer, a lightly doped drain is formed on and in the substrate. Then, a spacer is formed on the liner layer. Thereafter, a proper process is used to introduce ions into the lightly doped drain, and then a source/drain region is completed. The steps with follow include annealing the source/drain region and removing the spacer. Subsequently, an epi-silicon layer is formed on the lightly doped drain region, the source/drain region and the top surface of the conductor layer.

Abstract: A method for fabricating a landing pad is described in which a transistor is formed on the substrate, wherein the transistor comprises a gate and source/drain regions at both sides of the gate in the substrate. A cap layer and a spacer are formed on the gate and at the sidewall of the gate respectively. A protective layer is formed to cover the substrate. The protective layer is then defined to form an opening to expose the source/drain region. A polysilicon landing pad is then formed in the opening and on the protective layer at the periphery of the opening. Silicidation is then conducted on the polysilicon landing pad to form a metal silicide landing pad and to destroy any native oxide at the source/drain region.