Abstract: In one example, the disclosure is directed to error-correcting code techniques for managing data by a host device. In some examples, in writing the data, a host device receives parity data, data and one or more error pointers from a storage device. Each respective error pointer references a location of a respective data sector of the data that contains an error. The host device determines, based at least in part on the one or more error pointers, a first data sector of the data that contains an error. The host device recovers, based at least in part on the parity data, the data, and the one or more error pointers, the first data sector.

Abstract: In one example, the disclosure is directed to error-correcting code techniques for managing data in a hard drive. In some examples, a controller of a hard disk drive may cause data including a data band and an associated parity sector to be retrieved from non-volatile memory. The data band may include a number of virtual data tracks, and each virtual data track may include a respective plurality of sectors. The controller may determine that at least one sector of the respective plurality of sectors includes an error that renders the data in the at least one sector unreadable by the controller. The controller may send the data including the data band and the associated parity sector to a host device.

Abstract: Data storage devices using a two-level ECC scheme are described. Embodiments of the invention allow the recovery of sectors in a squeezed group of tracks in a that includes both a single track level ECC scheme and a track band ECC scheme that functions across the set of tracks in the band. The track band ECC scheme uses additional parity information calculated using input data from multiple tracks to allow correction across tracks.

Abstract: Data storage devices are described with an ECC system that generate additional on-demand ECC information for a previously written track to provide for correction of data errors in the track and thereby avoid having to rewrite the track. Embodiments of the invention address the squeeze-error problem that arises when writing the next (second) track in a sequence causes errors to be introduced in the adjacent previously written (first) track. In alternative embodiments the existence of the data errors in the first track can be detected by reading the track or by estimating the number of likely errors using head position data measured while writing the first and second tracks. The additional on-demand ECC information can be written on any track that is available.

Abstract: ECC Encoders that process packets of p bits (with p>1) in a data block in parallel and generate a set of N parity/check bits that are stored along with the original data in the memory block. Encoders according to the invention can be used to create a nonvolatile NAND Flash memory write cache with BCH-ECC for use in a disk drive that can speed up the response time for some write operations. Encoder embodiments of the invention use Partial-Parity Feedback along with a XOR-Matrix Logic Module, which calculates N output bits from p input bits, and a Shift Register Module that accumulates N check bits. The XOR-Matrix Logic Module is designed using a precalculated Matrix of p×N bits, which is translated into VHDL design language to generate the hardware gates. High-Order p-bit Partial-Parity Feedback improves over LFSR designs and achieves Minimal Critical Path Length:=p.

Abstract: Data storage devices are described with an ECC system that generate additional on-demand ECC information for a previously written track to provide for correction of data errors in the track and thereby avoid having to rewrite the track. Embodiments of the invention address the squeeze-error problem that arises when writing the next (second) track in a sequence causes errors to be introduced in the adjacent previously written (first) track. In alternative embodiments the existence of the data errors in the first track can be detected by reading the track or by estimating the number of likely errors using head position data measured while writing the first and second tracks. The additional on-demand ECC information can be written on any track that is available.

Abstract: Data storage devices using a two-level ECC scheme are described. Embodiments of the invention allow the recovery of sectors in a squeezed group of tracks in a that includes both a single track level ECC scheme and a track band ECC scheme that functions across the set of tracks in the band. The track band ECC scheme uses additional parity information calculated using input data from multiple tracks to allow correction across tracks.

Abstract: A technique for recovering of “squeezed” sectors in a set of sequential sectors such as are used in Shingled Magnetic Recording (SMR) is described. Embodiments of the invention use a programmable erased sector recovery scheme, which is a concatenation of a “Cauchy-type” track erasure correction code, together with a media-error correction code that generates N-weighted parity-sectors per track and is capable of replacing up to N-erased sectors per track in any possible combination.

Abstract: A disk drive is described with a single servo master timer that is used to control timing critical signals such as servo gate, SAM windows, channel power save, PREAMP power save and so on. The master timer is adjusted to compensate for SAM detection errors (early, late or missed) and provides improved servo timing quality. In an embodiment the adjustable master timer can be selectably clocked by either the DLC/DSW clock or the system clock.

Abstract: A disk drive is described with a single servo master timer that is used to control timing critical signals such as servo gate, SAM windows, channel power save, PREAMP power save and so on. The master timer is adjusted to compensate for SAM detection errors (early, late or missed) and provides improved servo timing quality. In an embodiment the adjustable master timer can be selectably clocked by either the DLC/DSW clock or the system clock.

Abstract: A technique for recovering of “squeezed” sectors in a set of sequential sectors such as are used in Shingled Magnetic Recording (SMR) is described. Embodiments of the invention use a programmable erased sector recovery scheme, which is a concatenation of a “Cauchy-type” track erasure correction code, together with a media-error correction code that generates N-weighted parity-sectors per track and is capable of replacing up to N-erased sectors per track in any possible combination.

Abstract: A “write-squeeze-verify” method is used for verification of the data that has been written in the annular bands of a shingled magnetic recording disk drive. The writing of data along a track overwrites a portion of the previously written track and thus “squeezes” the data of the previously written track to thereby form a “shingled data track” (SDT). The data in each SDT is read back and verified by an error correction check using error correction bits associated with the data written in the SDT, or by comparing the readback data with the data stored in memory. If the data read back is not verified, a write error counter is incremented and a write error frequency is calculated. One or more attempts to write the data can be performed. If the data in the SDT cannot be verified after the attempted rewrite(s), then a “re-try fail” is reported.

Abstract: A “write-squeeze-verify” method is used for verification of the data that has been written in the annular bands of a shingled magnetic recording disk drive. The writing of data along a track overwrites a portion of the previously written track and thus “squeezes” the data of the previously written track to thereby form a “shingled data track” (SDT). The data in each SDT is read back and verified by performing an error correction check using error correction bits associated with the data written in the SDT, or by comparing the readback data with the data stored in memory. If the data read back is not verified, a write error counter is incremented and a write error frequency is calculated. One or more attempts to write the data can be performed. If the data in the SDT cannot be verified after the attempted rewrite(s), then a “re-try fail” is reported.

Abstract: A method and system are described for performing an arithmetic operation such as multiplication or division of a fixed point variable measured at runtime by a floating point constant known at compile-time. The floating point constant is converted into a mantissa and a base-2 exponent at compile-time. The mantissa and exponent are preferably combined into a single unit (a word) of memory. At runtime either single multiplication and accumulation or matrix multiplication and accumulation is preferably achieved by a microprocessor or DSP instruction designed to use the mantissa-exponent pairs stored in a word of memory. The microprocessor instruction multiplies a fixed point runtime variable x by the mantissa and the result is shifted to the right or left as indicated by the exponent, which is preferably a 2's complement number. The complete instruction sequence to perform the multiplication can be made reentrant and can be pipelined.

Abstract: A method, apparatus and program storage device that provides a shift process with saturation for digital signal processor operations are disclosed. An instruction is generated for shifting an operand to either maximum or the minimum value depending on the bit of data input when saturation occurs. A saturation detection circuit is combined with an arithmetic shifter and a final decision multiplexor. The final decision multiplexor receives the output from the arithmetic shifter and the saturated value from the saturation circuit. When saturation is detected by the saturation detection circuit, the final decision multiplexor selects the saturate minimum or the saturate maximum depending on whether the MSB of the data in equals one or zero, respectively.

Abstract: Systems and methods are provided for performing error correction decoding. The coefficients of the error locator polynomial are iteratively determined for each codeword using a modular implementation of a single recursion key-equation solver algorithm. According to this implementation, modules are used to calculate the current and previous coefficients of the error locator polynomial. One module is used for each correctable error. The modular single recursion implementation is programmable, because the number of modules can be easily changed to correct any number of correctable errors. Galois field tower arithmetic can be used to calculate the inverse of an error term. Galois field tower arithmetic greatly reduces the size of the inversion unit. The latency time can be reduced by placing the computations of the inverse error term outside the critical path of the error locator polynomial algorithm.

Abstract: A digital filter instruction and filter implementing the filter instruction are disclosed. The filter instruction synthesizes a digital filter and includes an instruction field, a tap length field, a coefficient address field, a data header address field, a clear accumulator bit and an update bit. The filter instruction a concise instruction format to significantly decrease memory required, allow for instruction pipelining without branch penalty, and uses a circular buffer for the data so the data address pointer is only needed to be updated for the next input sample. The filter instruction may be used to implement FIR or IIR filters by using the options of pre-clear accumulator or pre/post storing accumulator results.

Abstract: A magnetic disk for a hard disk drive comprising a plurality of physical sector sizes is disclosed. The magnetic disk includes a first sector size area physically formatted according to a first physical sector size and a second sector size area physically formatted according to a second physical sector size different from the first sector size by a multiple of the first sector size wherein the second sector size can be presented externally as multiple sectors of said first sector size.

Abstract: Techniques are provided for performing Galois field arithmetic to detect errors in digital data stored on disks. Two 12-bit numbers or two 10-bit numbers are multiplied together in Galois field using tower arithmetic. In the 12-bit embodiment, a base field GF(2) is first extended to GF(23), GF(23) is extended to a first quadratic extension GF(26), and GF(26) is extended to a second quadratic extension GF(212). In the 10-bit embodiment, the base field GF(2) is first extended to GF(25), and GF(25) is extended to a quadratic extension GF(210). Each of the extensions for the 10-bit and 12-bit embodiments is performed using an irreducible polynomial. All of the polynomials used to generate the first and the second quadratic extensions of the Galois field are in the form x2+x+K, where K is an element of the ground field whose absolute trace equals 1.

Abstract: A combined encoder/syndrome generator is provided that has a reduced delay. The combined encoder/syndrome generator generates check symbols during an encoding process and error syndromes during a decoding process. The combined encoder/syndrome generator has two or more blocks. The output of each block is fed as an input into a subsequent block. Each block can perform computations in parallel to reduce the delay of the encoding system.