Abstract: A circuit that allows selection of a power source among a plurality of power sources is disclosed. In an embodiment, either one or both voltage sources Vaux and Vapp may be available in a system. If both sources are available, then the circuit enables the system to use source Vaux. However, if only one of the two sources is available, then the circuit enables the system to use that available source.

Abstract: A power distribution system comprises a flexible power connector, a printed circuit board, a power supply, and a processor mounted on the printed circuit board. The flexible power connector comprises a first end electrically connected to the processor and a second end electrically connected to the power supply. The flexible power connector is configured with a length so that the power supply is in a spaced relationship relative to the processor and the flexible power connector includes a plurality of stacked layers arranged generally parallel to each other for distributed power transmission. These layers include at least two ground layers and at least one power layer. The power layer is sandwiched between two of the at least two ground layers.

Abstract: The present invention provides systems and methods for performing frequency margin testing of a computer system, such as a server. A system of the invention can include a controller, e.g., a BMC, internal to the computer system and a digital frequency synthesizer that can communicate with the controller and can apply clock frequency to marginable components of the computer system. In response to commands from the controller, the synthesizer generates one or more test frequencies that are applied to one or more of the marginable components. The response of the system to each of the test frequencies is then monitored.

Abstract: A method of transmitting data through an I2C router from a source port to a destination port, the method comprising: receiving data in a first I2C source port buffer of the I2C router; capturing the I2C destination port before the first I2C source port buffer has overflowed; and transmitting the data from the first I2C source port buffer to the I2C destination port while restricting transmission from the second I2C source port buffer to the I2C destination port.

Abstract: Embodiments of the present invention provide a system and method for detecting if a device is coupled to an inter-integrated circuit (I2C) router and/or for resetting the device. The I2C router comprises a first I2C bus port having a presence line and/or a reset line. The I2C router further comprises a control logic coupled to and/or distributed within the first I2C bus port. The control logic may determine if a device is coupled to the I2C router as a function of a state of the presence line. The control logic may also determine if a reset condition exists. If a reset condition exists, the control logic changes the state of the reset line, thereby causing the device to reset itself.

Abstract: A method of recovering overflowed data at a first I2C source port buffer on an I2C router having a second I2C source port buffer and a destination port I2C bus. The method comprises: requesting resend of said overflowed data to the first I2C source port buffer; receiving the overflowed data at the first I2C source port buffer; capturing the destination port I2C bus and transmitting all data from the first I2C source port buffer to the destination port I2C bus.

Abstract: Embodiments of the present invention provide a system for analysis of an inter-integrated circuit router. The inter-integrated circuit router comprises an internal bus comprising a plurality of debug lines, a plurality of bus ports wherein at least one bus port comprises a bus port analysis line, and a control logic comprising a control logic analysis line. The inter-integrated circuit router further comprises a debug connector coupled to said debug lines, said bus port analysis line and said control logic analysis line.

Abstract: The present invention provides a convenient and efficient integrated circuit router error management system and method. In one embodiment an inter-integrated circuit router error management system comprises a high-speed internal bus, an inter-integrated circuit port, a high-speed external port and an error register. The high-speed internal bus communicates information. The inter-integrated circuit port is coupled to the high-speed internal bus and the inter-integrated circuit port provides an interface for communicating information with an inter-integrated circuit bus segment. The high-speed external port is coupled to the high-speed internal bus and the high-speed external port provides an interface to an external high-speed bus. The error register is coupled to the inter-integrated circuit port and the error register captures errors in communication operations.

Abstract: An inter-integrated circuit port for providing increased security. An electrical connector for communicative coupling to an inter-integrated circuit bus is provided. A controller coupled to the electrical connector operates to control data communication through the electrical connector based on control information. A mask coupled to the controller provides the control information to the controller.

Abstract: An inter-integrated circuit router for supporting independent transmission rates. An internal bus is operable to transmit data at a first transmission rate. An inter-integrated circuit port is coupled to the internal bus, wherein the inter-integrated circuit port comprises a first buffer and is configured for coupling to an external inter-integrated circuit bus operable to transmit data at a second transmission rate. A port is coupled to the internal bus and is configured for coupling to an external bus operable to transmit data at a third transmission rate. The first buffer is operable to buffer data transmitted between the internal bus and the external inter-integrated bus provided the first transmission rate is different than the second transmission rate.

Abstract: A test assembly comprises a backplane interface to a backplane having at least one channel that further comprises a bi-directional two wire bus, a display interface capable of coupling to a display, and a control element. The control element is coupled to the backplane interface and the display interface. The control element is capable of snooping the bi-directional two wire bus and converting data on the bi-directional two wire bus to a readable format for display via the display interface.

Abstract: A circuit that allows selection of a power source among a plurality of power sources is disclosed. In an embodiment, either one or both voltage sources Vaux and Vapp may be available in a system. If both sources are available, then the circuit enables the system to use source Vaux. However, if only one of the two sources is available, then the circuit enables the system to use that available source.

Abstract: A converter assembly comprises a backplane interface to a backplane compliant with a first open architecture modular computing system standard, a component interface capable of coupling to a component compliant with a second open architecture modular computing system standard, and a control element. The control element is coupled between the backplane interface and the component interface and is capable of programmably routing connection lines and signals between the component interface and the backplane interface.

Abstract: An electrical device having an enclosure in which noise is parasitically induced in a wire located in the interior of the enclosure is disclosed. The electrical device has an entry connector for mating the wire with an external connector at which a transmission line terminates for preventing the induced noise from being emitted from the device enclosure via the transmission line. The electrical device comprises a printed circuit board (PCB) adapted to be mounted adjacent to an opening in a wall of the enclosure, a receptacle, integral with the PCB, configured to mate with the external connector, a first conductive path coupling the transmission line with the wire when mated, and capacitors mounted on the printed circuit board radially disposed around the receptacle and adapted to be electrically coupled to the external connector when mated. The electrical device further comprises a second conductive path coupling the capacitors to a low potential sink.