Abstract: Methods are provided for fabricating a semiconductor junction. A first semiconductor structure is selectively grown in a nanotube, which extends laterally over a substrate, from a seed extending within the nanotube. The seed is removed to expose the first semiconductor structure and create a cavity in the nanotube. A second semiconductor structure is selectively grown in the cavity from the first semiconductor structure, thereby forming a semiconductor junction between the first and second structures.

Abstract: Methods are provided for fabricating a semiconductor junction. A first semiconductor structure is selectively grown in a nanotube, which extends laterally over a substrate, from a seed extending within the nanotube. The seed is removed to expose the first semiconductor structure and create a cavity in the nanotube. A second semiconductor structure is selectively grown in the cavity from the first semiconductor structure, thereby forming a semiconductor junction between the first and second structures.

Abstract: Methods are provided for fabricating a semiconductor junction. A first semiconductor structure is selectively grown in a nanotube, which extends laterally over a substrate, from a seed extending within the nanotube. The seed is removed to expose the first semiconductor structure and create a cavity in the nanotube. A second semiconductor structure is selectively grown in the cavity from the first semiconductor structure, thereby forming a semiconductor junction between the first and second structures.

Abstract: Embodiments include various plasmonic devices. The plasmonic devices may include: a conductor layer, an insulator layer, and a hybrid layer. The conductor layer may include an input segment, a manipulation segment, and an output segment. The conductor layer is disposed on a surface of a substrate. The insulator layer is disposed on a top surface of the conductor layer. The hybrid layer is disposed on top surface of insulator layer. The manipulation hybrid layer may include an input segment and a semiconductor segment, output segment on one or two or multiple sides of the active channel. When a positive gate voltage is applied between the conductor segment of the conductor layer and the semiconductor segment of the hybrid layer, the semiconductor segment is turned into accumulated semiconductor, surface plasmons polaritons (SPP) propagate along the insulator layer freely. When the gate voltage is negative, the semiconductor segment is turned into depleted semiconductor, and SPP propagation ceases.

Abstract: Embodiments include various plasmonic devices. The plasmonic devices may include: a conductor layer, an insulator layer, and a hybrid layer. The conductor layer may include an input segment, a manipulation segment, and an output segment. The conductor layer is disposed on a surface of a substrate. The insulator layer is disposed on a top surface of the conductor layer. The hybrid layer is disposed on top surface of insulator layer. The manipulation hybrid layer may include an input segment and a semiconductor segment, output segment on one or two or multiple sides of the active channel. When a positive gate voltage is applied between the conductor segment of the conductor layer and the semiconductor segment of the hybrid layer, the semiconductor segment is turned into accumulated semiconductor, surface plasmons polaritons (SPP) propagate along the insulator layer freely. When the gate voltage is negative, the semiconductor segment is turned into depleted semiconductor, and SPP propagation ceases.

Abstract: Methods are provided for fabricating a semiconductor junction. A first semiconductor structure is selectively grown in a nanotube, which extends laterally over a substrate, from a seed extending within the nanotube. The seed is removed to expose the first semiconductor structure and create a cavity in the nanotube. A second semiconductor structure is selectively grown in the cavity from the first semiconductor structure, thereby forming a semiconductor junction between the first and second structures.

Abstract: The local bending of a silicon nanowire induces tensile strain in the wire due to the stretching of the silicon lattice. This in turn enhances the mobility of the free carriers (electrons) in the direction of transport along the wire. Thus, for example, when Gate-All-Around MOSFETs are fabricated along the nanowire, the mobility enhancement will translate into an improvement in the performance (current drive, speed) of the silicon nanowire MOSFETs. In summary, a semiconductor device comprises a substrate and a nanowire in connection with the substrate at a drain and at a source region, and the nanowire is bent to achieve enhanced mobility of charge carriers.

Abstract: The present invention exploits the impact ionization induced by drain voltage increase and the onset of a bipolar parasitic in an ?-gate field effect metal oxide insulator transistor (called PI-MOS), in order to obtain a memory effect and abrupt current switching.

Abstract: The invention relates to a light phase modulator, which is based on a multi-gate transistor.

Abstract: The invention relates to methods for manufacturing semiconductor devices. Processes are disclosed for implementing suspended single crystal silicon nano wires (NWs) using a combination of anisotropic and isotropic etches and spacer creation for sidewall protection. The core dimensions of the NWs are adjustable with the integration sequences: they can be triangular, rectangular, quasi-circular, or an alternative polygonal shape. Depending on the length of the NWs, going from the sub-micron to millimeter range, the NWs may utilize support from anchors to the side, during certain processing steps. By changing the lithographic dimensions of the anchors compared to the NWs, the anchors may be reduced or eliminated during processing. The method covers, among other things, the integration of Gate-All-Around NW (GAA-NW) MOSFETs on a bulk semiconductor.