Abstract: According to at least some example embodiments of the inventive concepts, an RC oscillator includes an oscillator core including a timing-circuit that includes a plurality of matched current sources, a plurality of capacitors, and a resistor, a first continuous time comparator, and a Schmitt trigger; and an analog circuit connected to the oscillator core including a second continuous time comparator representing a replica of the first continuous time comparator, and an EX-OR gate, wherein the analog circuit is configured to pass a clock signal of the oscillator core through the second continuous time comparator and obtaining a delayed clock signal representing a comparator delay, extract the comparator delay of the first continuous time comparator based on feeding the clock signal and the obtained delayed clock signal to the EX-OR gate, and charge the plurality of capacitors connected to the first continuous time comparator.

Abstract: According to at least some example embodiments of the inventive concepts, an RC oscillator includes an oscillator core including a timing-circuit that includes a plurality of matched current sources, a plurality of capacitors, and a resistor, a first continuous time comparator, and a Schmitt trigger; and an analog circuit connected to the oscillator core including a second continuous time comparator representing a replica of the first continuous time comparator, and an EX-OR gate, wherein the analog circuit is configured to pass a clock signal of the oscillator core through the second continuous time comparator and obtaining a delayed clock signal representing a comparator delay, extract the comparator delay of the first continuous time comparator based on feeding the clock signal and the obtained delayed clock signal to the EX-OR gate, and charge the plurality of capacitors connected to the first continuous time comparator.

Abstract: The inventive concepts relate to methods for duty cycle correction of an input signal and circuits thereof. The method comprising following operations of generating, a plurality of intermediate delayed input signals, each delayed by at least a unit delay, through a delay line driven by the input signal, selecting from among the plurality of delayed input signals, through a first control signal, where the selection is based on number of unit delays in the input signal, generating at least an incremented duty signal and a decremented duty signal based on the selected delayed signals and the input signal, generating, a corrected duty cycle based on the selection of at least one of: the incremented duty cycle or decremented duty cycle by providing a second control signal. The inventive concepts offer low power consumption and low area for correction or adjustment of the duty cycle of the input signal with higher probability or guaranteed monotonicity.

Abstract: The inventive concepts relate to methods for duty cycle correction of an input signal and circuits thereof. The method comprising following operations of generating, a plurality of intermediate delayed input signals, each delayed by at least a unit delay, through a delay line driven by the input signal, selecting from among the plurality of delayed input signals, through a first control signal, where the selection is based on number of unit delays in the input signal, generating at least an incremented duty signal and a decremented duty signal based on the selected delayed signals and the input signal, generating, a corrected duty cycle based on the selection of at least one of: the incremented duty cycle or decremented duty cycle by providing a second control signal. The inventive concepts offer low power consumption and low area for correction or adjustment of the duty cycle of the input signal with higher probability or guaranteed monotonicity.

Abstract: An electronic system having a linear voltage regulator and method of operating the linear voltage regulator. A linear voltage regulator of an electronic system has at least three ballast devices. The method of operating includes producing a voltage at an output terminal that is electrically coupled to a node of a first one of the three or more ballast devices; receiving a power mode indication; activating a first additional ballast device of the linear voltage regulator to add first additional capacitance to a load corresponding to the power mode; generating one or more successively delayed ballast control signals based at least in part on the power mode indication; and activating, using the successively delayed ballast control signals, second additional ballast devices of the linear voltage regulator to add second capacitances to the load of the linear voltage regulator.

Abstract: An electronic system having a linear voltage regulator and method of operating the linear voltage regulator. A linear voltage regulator of an electronic system has at least three ballast devices. The method of operating includes producing a voltage at an output terminal that is electrically coupled to a node of a first one of the three or more ballast devices; receiving a power mode indication; activating a first additional ballast device of the linear voltage regulator to add first additional capacitance to a load corresponding to the power mode; generating one or more successively delayed ballast control signals based at least in part on the power mode indication; and activating, using the successively delayed ballast control signals, second additional ballast devices of the linear voltage regulator to add second capacitances to the load of the linear voltage regulator.

Abstract: A linear voltage regulator including a pass element, an error amplifier, and in-rush current protection (ICP) circuitry. The pass element is configured to produce an output voltage across a capacitor based on a received input voltage. The error amplifier is configured to output a control voltage based at least in part on the output voltage and a reference voltage. The control voltage is used to control a flow of output current through the pass element. The ICP circuitry is coupled to the pass element and the error amplifier and configured to maintain the output current below a threshold level while charging the capacitor from a discharged state to the output voltage.