Patents by Inventor Kishan Shenoi

Kishan Shenoi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20130077642
    Abstract: Systems and methods are disclosed for utilizing slave (receive) time-stamp clock rates that are different from master (sender) time-stamp clock rates to randomize and thereby reduce systematic time-stamp granularity errors in the communication of network packets. The slave (receive) time-stamp clock rate for some embodiments is set to be a fixed value that has a relationship with the master (sender) time-stamp clock rate such that the ratio of the slave (receive) clock rate to the master (sender) clock rate is a rational number. Other embodiments use a time-varying frequency for the slave (receive) time-stamp clock rate to randomize the slave (receive) time-stamp clock with respect to the master (sender) time-stamp clock. Additional time-stamps can also be generated using a slave (receive) time-stamp clock having a rate set to equal the rate of the master (sender) time-stamp clock signal.
    Type: Application
    Filed: April 9, 2012
    Publication date: March 28, 2013
    Inventors: Charles A. Webb, III, Kishan Shenoi
  • Patent number: 8385212
    Abstract: A latency floor between two nodes of a packet-switched network is estimated using transit times of a group of packets traversing the two nodes. In particular, a periodically generated histogram of packet transit times is used to estimate the latency floor. In some packet-switched networks, the behavior of some network elements changes drastically when the network is congested. Because latency floor cannot be accurately estimated under such conditions, packet transit times collected during a congested state of the network are discarded.
    Type: Grant
    Filed: December 7, 2009
    Date of Patent: February 26, 2013
    Assignee: Symmetricom, Inc.
    Inventors: George P. Zampetti, Kishan Shenoi
  • Patent number: 8379151
    Abstract: A method includes synchronizing audio and video streams including aligning the audio path and the video path by introducing a variable delay to the audio path or the video path to substantially equalize the end-to-end delay of both the audio path and the video path. An apparatus includes a digital to analog convertor for synchronizing audio and video where the audio path and the video path are aligned by introducing a variable delay to the audio path or the video path to substantially equalize the end-to-end delay of both the audio path and the video path.
    Type: Grant
    Filed: March 24, 2011
    Date of Patent: February 19, 2013
    Assignee: Floreat, Inc.
    Inventor: Kishan Shenoi
  • Patent number: 8274999
    Abstract: Packet network performance is assessed using transit delay metrics and compliance masks generated at various evaluation nodes of the network. The evaluation nodes may employ network probes that make precise measurements of transit delays and thereby of transit delay variations. Based on the assessments, a master may be added to the network or relocated within the network, rate of timing packets generated by the master may be adjusted up or down, or oscillators used at the slaves may be upgraded.
    Type: Grant
    Filed: July 2, 2010
    Date of Patent: September 25, 2012
    Assignee: Symmetricom, Inc.
    Inventors: Kishan Shenoi, George P. Zampetti, Lee Cosart
  • Publication number: 20110234200
    Abstract: A method includes monitoring a fill in an adaptive slip buffer of a digital to analog convertor; adjusting a number of samples that are read from the adaptive slip buffer per page as a function of the fill; and reading the number of samples from the adaptive slip buffer. An apparatus includes a digital to analog convertor including an adaptive slip buffer and a read address generator coupled to the adaptive slip buffer, wherein the read address generator includes an increment control that adjusts a number of samples that are read from the adaptive slip buffer per page as a function of fill of the adaptive slip buffer.
    Type: Application
    Filed: March 24, 2011
    Publication date: September 29, 2011
    Inventor: Kishan Shenoi
  • Publication number: 20110234902
    Abstract: A method includes synchronizing audio and video streams including applying a time-stamp to a block of a audio buffer in an audio path; applying a time-stamp to a block of a video buffer in a video path; reading the block from the audio buffer; reading the block from the video buffer; and aligning the audio path and the video path by introducing a variable delay to one member selected from the group consisting of the audio path or the video path to substantially equalize the end-to-end delay of both the audio path and the video path.
    Type: Application
    Filed: March 24, 2011
    Publication date: September 29, 2011
    Inventor: Kishan Shenoi
  • Publication number: 20110235500
    Abstract: A method includes operating an integrated echo canceller and speech codec for voice-over internet protocol. An apparatus includes an echo canceller and a speech codec, wherein the speech codec includes a decoder and an encoder, and wherein the echo canceller and the speech codec are integrated for voice-over-internet protocol.
    Type: Application
    Filed: March 24, 2011
    Publication date: September 29, 2011
    Inventor: Kishan Shenoi
  • Publication number: 20110134766
    Abstract: A latency floor between two nodes of a packet-switched network is estimated using transit times of a group of packets traversing the two nodes. In particular, a periodically generated histogram of packet transit times is used to estimate the latency floor. In some packet-switched networks, the behavior of some network elements changes drastically when the network is congested. Because latency floor cannot be accurately estimated under such conditions, packet transit times collected during a congested state of the network are discarded.
    Type: Application
    Filed: December 7, 2009
    Publication date: June 9, 2011
    Inventors: George P. Zampetti, Kishan Shenoi
  • Publication number: 20110122871
    Abstract: Packet network performance is assessed using transit delay metrics and compliance masks generated at various evaluation nodes of the network. The evaluation nodes may employ network probes that make precise measurements of transit delays and thereby of transit delay variations. Based on the assessments, a master may be added to the network or relocated within the network, rate of timing packets generated by the master may be adjusted up or down, or oscillators used at the slaves may be upgraded.
    Type: Application
    Filed: July 2, 2010
    Publication date: May 26, 2011
    Inventors: Kishan SHENOI, George P. ZAMPETTI, Lee COSART
  • Publication number: 20110122775
    Abstract: Routes of a packet network are analyzed according to various transit delay metrics. Preferred packet network routes are selected between source and destination based on these metrics. In packet networks employing boundary clocks and transparent clocks, faulty boundary clocks and faulty transparent clocks are identified using the metrics.
    Type: Application
    Filed: July 2, 2010
    Publication date: May 26, 2011
    Inventors: George P. ZAMPETTI, Kishan SHENOI
  • Patent number: 7894489
    Abstract: Methods and apparatus for a play-out buffer that may adjust offsets between clocks of two ends of a network link with an adaptive play-out buffer and adaptive clock control. The play-out buffer is a circular jitter buffer that permits the absorption of a frequency offset using controlled slips between two nodes of a network. The play-out buffer also accommodates some wander introduced by the time-delay variation across the network. The adaptive clock control reduces the frequency offset between the clocks of the two nodes. In this manner, even though some offsets between two nodes would render communication inefficient, embodiments of the present invention allow the effects of these offsets to be mitigated, thus providing for a better quality coupling.
    Type: Grant
    Filed: June 12, 2006
    Date of Patent: February 22, 2011
    Assignee: Symmetricom, Inc.
    Inventor: Kishan Shenoi
  • Patent number: 7636022
    Abstract: Methods and apparatus are described for a play-out buffer. A method includes writing a data packet into a jitter buffer at a write address specified by a write address generator; incrementing the write address generator; generating the difference between the write address and a current read address specified by a read address generator; reading a data packet from the jitter buffer from the current read address specified by the read address generator; generating a new read address based on the difference between the write address and the current read address by the read address generator. An apparatus includes a jitter buffer; a write address generator for storing a write address; a read address generator for storing a current read address; a read address increment control; wherein the read address increment control sets the future read address based on the difference between the write address and the current read address.
    Type: Grant
    Filed: June 12, 2006
    Date of Patent: December 22, 2009
    Assignee: Symmetricom, Inc.
    Inventor: Kishan Shenoi
  • Patent number: 7535900
    Abstract: Methods and apparatus are described for providing multiple transmission bandwidth streams with differentiated quality of service on a inter-machine trunk. One approach includes time-division multiplexing. Another approach includes statistical multiplexing. Another approach includes packet segmentation. The approaches are commercially important because they significantly reduce time-delay variation.
    Type: Grant
    Filed: January 16, 2004
    Date of Patent: May 19, 2009
    Assignee: Symmetricom, Inc.
    Inventor: Kishan Shenoi
  • Patent number: 7382845
    Abstract: Systems and methods are described for distribution of synchronization in a packet switched local area network environment. A method for extracting network synchronization timing from a data transmission burst includes: recovering a clock during the data transmission burst; and then holding over the clock after the data transmission burst ceases. A method for inserting network synchronization timing into a data transmission burst includes encoding data using a time-base reference signal governed clock.
    Type: Grant
    Filed: December 16, 2002
    Date of Patent: June 3, 2008
    Assignee: Symmetricom, Inc.
    Inventor: Kishan Shenoi
  • Patent number: 7366286
    Abstract: Systems and methods are described for modified asymmetric digital subscriber line for use with long loops. A method includes modifying a digital signal processor including reallocating a portion of an original guard band to a modified downstream band and reallocating a portion of an original upstream band to a modified guard band. An apparatus includes a digital signal processor defining an expanded downstream band; and a high pass filter coupled to the digital signal processor to accommodate the expanded downstream band.
    Type: Grant
    Filed: December 20, 2002
    Date of Patent: April 29, 2008
    Assignee: Symmetricom, Inc
    Inventor: Kishan Shenoi
  • Patent number: 7349401
    Abstract: Systems and methods are described for deploying bonded G.shdsl links for ATM backhaul applications. A method includes transporting digital data including: coupling a first end of a plurality of unbundled network elements to a first modem; coupling a second end of the plurality of unbundled network elements to a second modem; providing the first modem with a first single stream of asynchronous transfer mode cells; sequence-cell division multiplexing to divide the first single stream of asynchronous transfer mode cells into a plurality of streams of cells at the first modem; transmitting the plurality of streams of cells to the second modem via the plurality of unbundled network elements; and sequence-cell division demultiplexing to bond the plurality of streams of cells into a second single stream of asynchronous transfer mode cells at the second modem.
    Type: Grant
    Filed: May 28, 2002
    Date of Patent: March 25, 2008
    Assignee: Symmetricom, Inc.
    Inventor: Kishan Shenoi
  • Patent number: 7310310
    Abstract: Systems and methods are described for bonding asynchronous transfer mode permanent virtual circuits using a multi-link segmentation and reassembly sublayer. A method includes: transforming a plurality of streams of asynchronous transfer mode cells into a stream of bonded asynchronous transfer mode cells, the plurality of streams of asynchronous transfer mode cells provided by a first plurality of permanent virtual circuits; demultiplexing the stream of bonded asynchronous transfer mode cells into a plurality of streams of inverse multiplexed bonded asynchronous transfer mode cells; and transmitting the plurality of streams of inverse multiplexed bonded asynchronous transfer mode cells to a remote location via a second plurality of permanent virtual circuits. The transmitted plurality of streams of inverse multiplexed bonded asynchronous transfer mode cells can be multiplexed and transformed into a plurality of multiplexed streams of asynchronous transfer mode cells after transmitting.
    Type: Grant
    Filed: February 21, 2003
    Date of Patent: December 18, 2007
    Assignee: Symmetricom, Inc.
    Inventors: Kishan Shenoi, Chi-Tao Chang
  • Publication number: 20070041324
    Abstract: Methods and apparatus are described for a play-out buffer. A method includes writing a data packet into a jitter buffer at a write address specified by a write address generator; incrementing the write address generator; generating the difference between the write address and a current read address specified by a read address generator; reading a data packet from the jitter buffer from the current read address specified by the read address generator; generating a new read address based on the difference between the write address and the current read address by the read address generator. An apparatus includes a jitter buffer; a write address generator for storing a write address; a read address generator for storing a current read address; a read address increment control; wherein the read address increment control sets the future read address based on the difference between the write address and the current read address.
    Type: Application
    Filed: June 12, 2006
    Publication date: February 22, 2007
    Inventor: Kishan Shenoi
  • Publication number: 20070036180
    Abstract: Methods and apparatus are described for a play-out buffer. A method includes writing a data packet into a jitter buffer at a write address specified by a write address generator; incrementing the write address generator; generating the difference between the write address and a current read address specified by a read address generator; reading a data packet from the jitter buffer from the current read address specified by the read address generator; generating a new read address based on the difference between the write address and the current read address by the read address generator. An apparatus includes a jitter buffer; a write address generator for storing a write address; a read address generator for storing a current read address; a read address increment control; wherein the read address increment control sets the future read address based on the difference between the write address and the current read address.
    Type: Application
    Filed: June 12, 2006
    Publication date: February 15, 2007
    Inventor: Kishan Shenoi
  • Patent number: 7161953
    Abstract: Systems and methods are described for bonding multiple G.shdsl links. A method includes transporting digital data including: coupling a first end of a plurality of unbundled network elements to a first modem; coupling a second end of the plurality of unbundled network elements to a second modem; applying a single signal to the first modem; time division multiplexing the single signal into a plurality of signals at the first modem; transmitting the plurality of signals to the second modem over the plurality of unbundled network elements; receiving the plurality of signals at the second modem; and time division demultiplexing the plurality of signals to combine the plurality of signals into a single synchronous signal at the second modem. Each of the plurality of unbundled network elements includes a G.shdsl link.
    Type: Grant
    Filed: May 28, 2002
    Date of Patent: January 9, 2007
    Assignee: Symmetricom, Inc.
    Inventor: Kishan Shenoi