Patents by Inventor Kishore Badari Atreya

Kishore Badari Atreya has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Compiler architecture for programmable application specific integrated circuit based network devices
    Patent number: 10466976
    Abstract: A processing network including a plurality of lookup and decision engines (LDEs) each having one or more configuration registers and a plurality of on-chip routers forming a matrix for routing the data between the LDEs, wherein each of the on-chip routers is communicatively coupled with one or more of the LDEs. The processing network further including an LDE compiler stored on a memory and communicatively coupled with each of the LDEs, wherein the LDE compiler is configured to generate values based on input source code that when programmed into the configuration registers of the LDEs cause the LDEs to implement the functionality defined by the input source code.
    Type: Grant
    Filed: November 6, 2017
    Date of Patent: November 5, 2019
    Assignee: Cavium, LLC
    Inventors: Ajeer Salil Pudiyapura, Kishore Badari Atreya, Ravindran Suresh
  • Software assisted hardware configuration for software defined network system-on-chip
    Patent number: 10282315
    Abstract: A software and hardware co-validation for SDN SoC method and system are able to be used to test software and hardware using PCIe (or another implementation) utilizing sockets and messages as the communication medium. An entire software stack as well as hardware are able to be tested. Additionally, multiple chips (SoCs) are able to be programmed at the same time, not just one, as in previous implementations.
    Type: Grant
    Filed: March 27, 2015
    Date of Patent: May 7, 2019
    Assignee: Cavium, LLC
    Inventors: Nimalan Siva, Premshanth Theivendran, Kishore Badari Atreya
  • COMPILER ARCHITECTURE FOR PROGRAMMABLE APPLICATION SPECIFIC INTEGRATED CIRCUIT BASED NETWORK DEVICES
    Publication number: 20180067728
    Abstract: A processing network including a plurality of lookup and decision engines (LDEs) each having one or more configuration registers and a plurality of on-chip routers forming a matrix for routing the data between the LDEs, wherein each of the on-chip routers is communicatively coupled with one or more of the LDEs. The processing network further including an LDE compiler stored on a memory and communicatively coupled with each of the LDEs, wherein the LDE compiler is configured to generate values based on input source code that when programmed into the configuration registers of the LDEs cause the LDEs to implement the functionality defined by the input source code.
    Type: Application
    Filed: November 6, 2017
    Publication date: March 8, 2018
    Inventors: Ajeer Salil Pudiyapura, Kishore Badari Atreya, Ravindran Suresh
  • Algorithm to achieve optimal layout of instruction tables for programmable network devices
    Patent number: 9870204
    Abstract: A processing network including a plurality of lookup and decision engines (LDEs) each having one or more configuration registers and a plurality of on-chip routers forming a matrix for routing the data between the LDEs, wherein each of the on-chip routers is communicatively coupled with one or more of the LDEs. The processing network further including an LDE compiler stored on a memory and communicatively coupled with each of the LDEs, wherein the LDE compiler is configured to generate values based on input source code that when programmed into the configuration registers of the LDEs cause the LDEs to implement the functionality defined by the input source code.
    Type: Grant
    Filed: March 31, 2015
    Date of Patent: January 16, 2018
    Assignee: Cavium, Inc.
    Inventors: Ajeer Salil Pudiyapura, Kishore Badari Atreya, Ravindran Suresh
  • Code processor to build orthogonal execution blocks for programmable network devices
    Patent number: 9864582
    Abstract: A processing network including a plurality of lookup and decision engines (LDEs) each having one or more configuration registers and a plurality of on-chip routers forming a matrix for routing the data between the LDEs, wherein each of the on-chip routers is communicatively coupled with one or more of the LDEs. The processing network further including an LDE compiler stored on a memory and communicatively coupled with each of the LDEs, wherein the LDE compiler is configured to generate values based on input source code that when programmed into the configuration registers of the LDEs cause the LDEs to implement the functionality defined by the input source code.
    Type: Grant
    Filed: March 31, 2015
    Date of Patent: January 9, 2018
    Assignee: Cavium, Inc.
    Inventors: Kishore Badari Atreya, Ajeer Salil Pudiyapura, Ravindran Suresh
  • Algorithm to derive logic expression to select execution blocks for programmable network devices
    Patent number: 9864583
    Abstract: A processing network including a plurality of lookup and decision engines (LDEs) each having one or more configuration registers and a plurality of on-chip routers forming a matrix for routing the data between the LDEs, wherein each of the on-chip routers is communicatively coupled with one or more of the LDEs. The processing network further including an LDE compiler stored on a memory and communicatively coupled with each of the LDEs, wherein the LDE compiler is configured to generate values based on input source code that when programmed into the configuration registers of the LDEs cause the LDEs to implement the functionality defined by the input source code.
    Type: Grant
    Filed: March 31, 2015
    Date of Patent: January 9, 2018
    Assignee: Cavium, Inc.
    Inventors: Ajeer Salil Pudiyapura, Kishore Badari Atreya, Ravindran Suresh
  • Code generator for programmable network devices
    Patent number: 9864584
    Abstract: A processing network including a plurality of lookup and decision engines (LDEs) each having one or more configuration registers and a plurality of on-chip routers forming a matrix for routing the data between the LDEs, wherein each of the on-chip routers is communicatively coupled with one or more of the LDEs. The processing network further including an LDE compiler stored on a memory and communicatively coupled with each of the LDEs, wherein the LDE compiler is configured to generate values based on input source code that when programmed into the configuration registers of the LDEs cause the LDEs to implement the functionality defined by the input source code.
    Type: Grant
    Filed: March 31, 2015
    Date of Patent: January 9, 2018
    Assignee: Cavium, Inc.
    Inventors: Ajeer Salil Pudiyapura, Kishore Badari Atreya, Ravindran Suresh
  • Compiler architecture for programmable application specific integrated circuit based network devices
    Patent number: 9836283
    Abstract: A processing network including a plurality of lookup and decision engines (LDEs) each having one or more configuration registers and a plurality of on-chip routers forming a matrix for routing the data between the LDEs, wherein each of the on-chip routers is communicatively coupled with one or more of the LDEs. The processing network further including an LDE compiler stored on a memory and communicatively coupled with each of the LDEs, wherein the LDE compiler is configured to generate values based on input source code that when programmed into the configuration registers of the LDEs cause the LDEs to implement the functionality defined by the input source code.
    Type: Grant
    Filed: March 31, 2015
    Date of Patent: December 5, 2017
    Assignee: Cavium, Inc.
    Inventors: Ajeer Salil Pudiyapura, Kishore Badari Atreya, Ravindran Suresh
  • Parser engine programming tool for programmable network devices
    Patent number: 9606781
    Abstract: A parser engine programming tool configured to receive an input file representing a directly connected cyclical graph or tree of decision points for parsing a range of incoming packet headers, automatically generate all possible paths within the graph and thereby the associated possible headers, and convert the determined paths/headers into a proper format for programming memory of a parser engine to parse the determined headers (represented by the paths).
    Type: Grant
    Filed: March 31, 2015
    Date of Patent: March 28, 2017
    Assignee: Cavium, Inc.
    Inventors: Kishore Badari Atreya, Ajeer Salil Pudiyapura, Ravindran Suresh
  • Algorithm to achieve optimal layout of decision logic elements for programmable network devices
    Patent number: 9582251
    Abstract: A processing network including a plurality of lookup and decision engines (LDEs) each having one or more configuration registers and a plurality of on-chip routers forming a matrix for routing the data between the LDEs, wherein each of the on-chip routers is communicatively coupled with one or more of the LDEs. The processing network further including an LDE compiler stored on a memory and communicatively coupled with each of the LDEs, wherein the LDE compiler is configured to generate values based on input source code that when programmed into the configuration registers of the LDEs cause the LDEs to implement the functionality defined by the input source code.
    Type: Grant
    Filed: March 31, 2015
    Date of Patent: February 28, 2017
    Assignee: Cavium, Inc.
    Inventors: Ajeer Salil Pudiyapura, Kishore Badari Atreya, Ravindran Suresh
  • SOFTWARE ASSISTED HARDWARE CONFIGURATION FOR SOFTWARE DEFINED NETWORK SYSTEM-ON-CHIP
    Publication number: 20160283413
    Abstract: A software and hardware co-validation for SDN SoC method and system are able to be used to test software and hardware using PCIe (or another implementation) utilizing sockets and messages as the communication medium. An entire software stack as well as hardware are able to be tested. Additionally, multiple chips (SoCs) are able to be programmed at the same time, not just one, as in previous implementations.
    Type: Application
    Filed: March 27, 2015
    Publication date: September 29, 2016
    Inventors: NIMALAN SIVA, PREMSHANTH THEIVENDRAN, KISHORE BADARI ATREYA
  • Co-verification—of hardware and software, a unified approach in verification
    Patent number: 9372772
    Abstract: A co-verification method and system are described herein. The co-verification method is able to verify software and hardware at the same time. Constraints are provided to a software compiler which generates programming values. The programming values and stimulus from a verification test bench are utilized to test a design such as a microprocessor.
    Type: Grant
    Filed: March 27, 2015
    Date of Patent: June 21, 2016
    Assignee: CAVIUM, INC.
    Inventors: Mohan Balan, Harish Krishnamoorthy, Nimalan Siva, Kishore Badari Atreya
  • CODE GENERATOR FOR PROGRAMMABLE NETWORK DEVICES
    Publication number: 20160139887
    Abstract: A processing network including a plurality of lookup and decision engines (LDEs) each having one or more configuration registers and a plurality of on-chip routers forming a matrix for routing the data between the LDEs, wherein each of the on-chip routers is communicatively coupled with one or more of the LDEs. The processing network further including an LDE compiler stored on a memory and communicatively coupled with each of the LDEs, wherein the LDE compiler is configured to generate values based on input source code that when programmed into the configuration registers of the LDEs cause the LDEs to implement the functionality defined by the input source code.
    Type: Application
    Filed: March 31, 2015
    Publication date: May 19, 2016
    Inventors: Ajeer Salil Pudiyapura, Kishore Badari Atreya, Ravindran Suresh
  • ALGORITHM TO ACHIEVE OPTIMAL LAYOUT OF INSTRUCTION TABLES FOR PROGRAMMABLE NETWORK DEVICES
    Publication number: 20160139898
    Abstract: A processing network including a plurality of lookup and decision engines (LDEs) each having one or more configuration registers and a plurality of on-chip routers forming a matrix for routing the data between the LDEs, wherein each of the on-chip routers is communicatively coupled with one or more of the LDEs. The processing network further including an LDE compiler stored on a memory and communicatively coupled with each of the LDEs, wherein the LDE compiler is configured to generate values based on input source code that when programmed into the configuration registers of the LDEs cause the LDEs to implement the functionality defined by the input source code.
    Type: Application
    Filed: March 31, 2015
    Publication date: May 19, 2016
    Inventors: Ajeer Salil Pudiyapura, Kishore Badari Atreya, Ravindran Suresh
  • ALGORITHM TO ACHIEVE OPTIMAL LAYOUT OF DECISION LOGIC ELEMENTS FOR PROGRAMMABLE NETWORK DEVICES
    Publication number: 20160139900
    Abstract: A processing network including a plurality of lookup and decision engines (LDEs) each having one or more configuration registers and a plurality of on-chip routers forming a matrix for routing the data between the LDEs, wherein each of the on-chip routers is communicatively coupled with one or more of the LDEs. The processing network further including an LDE compiler stored on a memory and communicatively coupled with each of the LDEs, wherein the LDE compiler is configured to generate values based on input source code that when programmed into the configuration registers of the LDEs cause the LDEs to implement the functionality defined by the input source code.
    Type: Application
    Filed: March 31, 2015
    Publication date: May 19, 2016
    Inventors: Ajeer Salil Pudiyapura, Kishore Badari Atreya, Ravindran Suresh
  • CODE PROCESSOR TO BUILD ORTHOGONAL EXECUTION BLOCKS FOR PROGRAMMABLE NETWORK DEVICES
    Publication number: 20160139893
    Abstract: A processing network including a plurality of lookup and decision engines (LDEs) each having one or more configuration registers and a plurality of on-chip routers forming a matrix for routing the data between the LDEs, wherein each of the on-chip routers is communicatively coupled with one or more of the LDEs. The processing network further including an LDE compiler stored on a memory and communicatively coupled with each of the LDEs, wherein the LDE compiler is configured to generate values based on input source code that when programmed into the configuration registers of the LDEs cause the LDEs to implement the functionality defined by the input source code.
    Type: Application
    Filed: March 31, 2015
    Publication date: May 19, 2016
    Inventors: Kishore Badari Atreya, Ajeer Salil Pudiyapura, Ravindran Suresh
  • PARSER ENGINE PROGRAMMING TOOL FOR PROGRAMMABLE NETWORK DEVICES
    Publication number: 20160139892
    Abstract: A parser engine programming tool configured to receive an input file representing a directly connected cyclical graph or tree of decision points for parsing a range of incoming packet headers, automatically generate all possible paths within the graph and thereby the associated possible headers, and convert the determined paths/headers into a proper format for programming memory of a parser engine to parse the determined headers (represented by the paths).
    Type: Application
    Filed: March 31, 2015
    Publication date: May 19, 2016
    Inventors: Kishore Badari Atreya, Ajeer Salil Pudiyapura, Ravindran Suresh
  • COMPILER ARCHITECTURE FOR PROGRAMMABLE APPLICATION SPECIFIC INTEGRATED CIRCUIT BASED NETWORK DEVICES
    Publication number: 20160139891
    Abstract: A processing network including a plurality of lookup and decision engines (LDEs) each having one or more configuration registers and a plurality of on-chip routers forming a matrix for routing the data between the LDEs, wherein each of the on-chip routers is communicatively coupled with one or more of the LDEs. The processing network further including an LDE compiler stored on a memory and communicatively coupled with each of the LDEs, wherein the LDE compiler is configured to generate values based on input source code that when programmed into the configuration registers of the LDEs cause the LDEs to implement the functionality defined by the input source code.
    Type: Application
    Filed: March 31, 2015
    Publication date: May 19, 2016
    Inventors: Ajeer Salil Pudiyapura, Kishore Badari Atreya, Ravindran Suresh
  • ALGORITHM TO DERIVE LOGIC EXPRESSION TO SELECT EXECUTION BLOCKS FOR PROGRAMMABLE NETWORK DEVICES
    Publication number: 20160139896
    Abstract: A processing network including a plurality of lookup and decision engines (LDEs) each having one or more configuration registers and a plurality of on-chip routers forming a matrix for routing the data between the LDEs, wherein each of the on-chip routers is communicatively coupled with one or more of the LDEs. The processing network further including an LDE compiler stored on a memory and communicatively coupled with each of the LDEs, wherein the LDE compiler is configured to generate values based on input source code that when programmed into the configuration registers of the LDEs cause the LDEs to implement the functionality defined by the input source code.
    Type: Application
    Filed: March 31, 2015
    Publication date: May 19, 2016
    Inventors: Ajeer Salil Pudiyapura, Kishore Badari Atreya, Ravindran Suresh