Abstract: A monolithic integrated circuit for use in a microwave backhaul system may comprise a plurality of microwave transceivers and outdoor-unit to indoor-unit (ODU/IDU) interface circuitry. The monolithic integrated circuit may be configurable into an all-outdoor configuration in which the ODU/IDU interface circuitry is disabled. The monolithic integrated circuit may be configurable into a split-indoor-and-outdoor configuration in which the ODU/IDU interface circuitry is enabled to communicate signals between an outdoor unit of the microwave backhaul system and an indoor unit of the microwave backhaul system. While the monolithic integrated circuit is configured in the split-indoor-and-outdoor configuration, the ODU/IDU interface circuitry may be configurable to operate in at least a non-stacking mode and a stacking mode.

Abstract: A microwave backhaul system may comprise a monolithic integrated circuit comprising an on-chip transceiver, digital baseband processing circuitry, and auxiliary interface circuitry. The on-chip transceiver may process a microwave signal from an antenna element to generate a first pair of quadrature baseband signals and convey the first pair of phase-quadrature baseband signals to the digital baseband processing circuitry. The auxiliary interface circuitry may receive one or more auxiliary signals from a source that is external to the monolithic integrated circuit and convey the one or more auxiliary signals to the digital baseband processing circuitry. The digital baseband processing circuitry may be operable to process signals to generate one or more second pairs of phase-quadrature digital baseband signals.

Abstract: Receiver architectures and methods of processing harmonic rich input signals employing harmonic suppression mixers are disclosed herein. The disclosed receivers, mixers, and methods enable a receiver to achieve the advantages of switching mixers while greatly reducing the mixer response to the undesired harmonics. A harmonic mixer can include a plurality of mixers coupled to an input signal. A plurality of phases of a local oscillator signal can be generated from a single local oscillator output. Each of the phases can be used to drive an input of one of the mixers. The mixer outputs can be combined to generate a frequency converted output that has harmonic rejection.

Abstract: A dual conversion receiver architecture that converts a radio frequency signal to produce a programmable intermediate frequency whose channel bandwidth and frequency can be changed using variable low-pass filtering to accommodate multiple standards for television and other wireless standards. The dual conversion receiver uses a two stage frequency translation and continual DC offset removal. The dual conversion receiver can be completely implemented on an integrated circuit with no external adjustments.

Abstract: A WiFi device, which utilizes full spectrum capture, captures signals over a wide spectrum including one or more WiFi frequency bands and extracts one or more WiFi channels from the captured signals. The AP analyzes the extracted WiFi channels and aggregates a plurality of blocks of WiFi channels to create one or more aggregated WiFi channels based on the analysis. The WiFi frequency bands comprise 2.4 GHz and 5 GHz WiFi frequency bands. The AP determines one or more characteristics of the extracted WiFi channels based on the analysis. The determined characteristics comprise noise, interference, fading and blocker information. The AP generates a channel map comprising at least the extracted one or more WiFi channels based on the determined characteristics. The AP dynamically and/or adaptively senses the extracted one or more WiFi channels and updates the determined characteristics of the extracted WiFi channels.

Abstract: A single receiver is operable to utilize full spectrum capture to capture signals over a wide spectrum comprising a plurality of WiFi frequency bands, extract one or more WiFi channels from said captured signals and aggregate a plurality of blocks of said WiFi channels to create one or more aggregated WiFi channels. The WiFi frequency bands include 2.4 GHz and 5 GHz WiFi frequency bands. A plurality of blocks of the WiFi channels may be aggregated from contiguous blocks of spectrum and/or non-contiguous blocks of spectrum in one or more of said plurality of WiFi frequency bands. One or more non-WiFi channels may be filtered out from the captured signals. One or more aggregated WiFi channels may be assigned to one or more WiFi enabled communication devices. At least a portion of the one or more aggregated WiFi channels may be dynamically assigned to one or more other WiFi enabled communication devices.

Abstract: A WiFi access point (AP) includes a receive radio frequency (RF) front end and a baseband processor that controls operation of the receive RF front end. The RF front end captures signals over a wide spectrum that includes a plurality of WiFi frequency bands (2.4 GHz and 5 GHz) and channelizes one or more WiFi channels from the captured signals. The baseband processor combines a plurality of blocks of WiFi channels to create one or more aggregated WiFi channels. The receive RF front end may be integrated on a first integrated circuit and the baseband processor may be integrated on a second integrated circuit. The first and second integrated circuits may be integrated on a single package. The RF front end and the baseband processor may be integrated on a single integrated circuit. The WiFi access point comprises a routing module that is communicatively coupled to the baseband processor.

Abstract: Receiver architectures and methods of processing harmonic rich input signals employing harmonic suppression mixers are disclosed herein. The disclosed receivers, mixers, and methods enable a receiver to achieve the advantages of switching mixers while greatly reducing the mixer response to the undesired harmonics. A harmonic mixer can include a plurality of mixers coupled to an input signal. A plurality of phases of a local oscillator signal can be generated from a single local oscillator output. Each of the phases can be used to drive an input of one of the mixers. The mixer outputs can be combined to generate a frequency converted output that has harmonic rejection.

Abstract: Receiver architectures and methods of processing harmonic rich input signals employing harmonic suppression mixers are disclosed herein. The disclosed receivers, mixers, and methods enable a receiver to achieve the advantages of switching mixers while greatly reducing the mixer response to the undesired harmonics. A harmonic mixer can include a plurality of mixers coupled to an input signal. A plurality of phases of a local oscillator signal can be generated from a single local oscillator output. Each of the phases can be used to drive an input of one of the mixers. The mixer outputs can be combined to generate a frequency converted output that has harmonic rejection.

Abstract: Receiver architectures and methods of processing harmonic rich input signals employing harmonic suppression mixers are disclosed herein. The disclosed receivers, mixers, and methods enable a receiver to achieve the advantages of switching mixers while greatly reducing the mixer response to the undesired harmonics. A harmonic mixer can include a plurality of mixers coupled to an input signal. A plurality of phases of a local oscillator signal can be generated from a single local oscillator output. Each of the phases can be used to drive an input of one of the mixers. The mixer outputs can be combined to generate a frequency converted output that has harmonic rejection.

Abstract: Receiver architectures and methods of processing harmonic rich input signals employing harmonic suppression mixers are disclosed herein. The disclosed receivers, mixers, and methods enable a receiver to achieve the advantages of switching mixers while greatly reducing the mixer response to the undesired harmonics. A harmonic mixer can include a plurality of mixers coupled to an input signal. A plurality of phases of a local oscillator signal can be generated from a single local oscillator output. Each of the phases can be used to drive an input of one of the mixers. The mixer outputs can be combined to generate a frequency converted output that has harmonic rejection.

Abstract: Receiver architectures and methods of processing harmonic rich input signals employing harmonic suppression mixers are disclosed herein. The disclosed receivers, mixers, and methods enable a receiver to achieve the advantages of switching mixers while greatly reducing the mixer response to the undesired harmonics. A harmonic mixer can include a plurality of mixers coupled to an input signal. A plurality of phases of a local oscillator signal can be generated from a single local oscillator output. Each of the phases can be used to drive an input of one of the mixers. The mixer outputs can be combined to generate a frequency converted output that has harmonic rejection.

Abstract: Receiver architectures and methods of processing harmonic rich input signals employing harmonic suppression mixers are disclosed herein. The disclosed receivers, mixers, and methods enable a receiver to achieve the advantages of switching mixers while greatly reducing the mixer response to the undesired harmonics. A harmonic mixer can include a plurality of mixers coupled to an input signal. A plurality of phases of a local oscillator signal can be generated from a single local oscillator output. Each of the phases can be used to drive an input of one of the mixers. The mixer outputs can be combined to generate a frequency converted output that has harmonic rejection.

Abstract: Receiver architectures and methods of processing harmonic rich input signals employing harmonic suppression mixers are disclosed herein. The disclosed receivers, mixers, and methods enable a receiver to achieve the advantages of switching mixers while greatly reducing the mixer response to the undesired harmonics. A harmonic mixer can include a plurality of mixers coupled to an input signal. A plurality of phases of a local oscillator signal can be generated from a single local oscillator output. Each of the phases can be used to drive an input of one of the mixers. The mixer outputs can be combined to generate a frequency converted output that has harmonic rejection.

Abstract: A receiver configured to selectively receive an RF signal from an operating band having a plurality of RF channels. The receiver is configured to upconvert the desired RF channel to an intermediate frequency (IF) greater than the RF channel frequencies. The upconverted RF channel is downconverted to baseband or a low IF. The receiver can perform channel selection by filtering the baseband or low IF signal. The baseband or low IF signal can be upconverted to a programmable output IF.

Abstract: A receiver can be configured to include an RF front end that is configured to downconvert a received signal to a baseband signal or a low Intermediate Frequency (IF) signal. The receiver can downconvert the desired signal from an RF frequency in the presence of numerous interference sources to a baseband or low IF signal for filtering and channel selection. The filtered baseband or low IF signal can be converted to a digital representation. The digital representation of the signal can be upconverted in the digital domain to a programmable IF frequency. The digital IF signal can be converted to an analog IF signal that can be processed by legacy hardware.

Abstract: Receiver architectures and methods of processing harmonic rich input signals employing harmonic suppression mixers are disclosed herein. The disclosed receivers, mixers, and methods enable a receiver to achieve the advantages of switching mixers while greatly reducing the mixer response to the undesired harmonics. A harmonic mixer can include a plurality of mixers coupled to an input signal. A plurality of phases of a local oscillator signal can be generated from a single local oscillator output. Each of the phases can be used to drive an input of one of the mixers. The mixer outputs can be combined to generate a frequency converted output that has harmonic rejection.

Abstract: A dual conversion receiver architecture that converts a radio frequency signal to produce a programmable intermediate frequency whose channel bandwidth and frequency can be changed using variable low-pass filtering to accommodate multiple standards for television and other wireless standards. The dual conversion receiver uses a two stage frequency translation and continual DC offset removal. The dual conversion receiver can be completely implemented on an integrated circuit with no external adjustments.

Abstract: A receiver can be configured to include an RF front end that is configured to downconvert a received signal to a baseband signal or a low Intermediate Frequency (IF) signal. The receiver can downconvert the desired signal from an RF frequency in the presence of numerous interference sources to a baseband or low IF signal for filtering and channel selection. The filtered baseband or low IF signal can be converted to a digital representation. The digital representation of the signal can be upconverted in the digital domain to a programmable IF frequency. The digital IF signal can be converted to an analog IF signal that can be processed by legacy hardware.

Abstract: A receiver configured to selectively receive an RF signal from an operating band having a plurality of RF channels. The receiver is configured to upconvert the desired RF channel to an intermediate frequency (IF) greater than the RF channel frequencies. The upconverted RF channel is downconverted to baseband or a low IF. The receiver can perform channel selection by filtering the baseband or low IF signal. The baseband or low IF signal can be upconverted to a programmable output IF.