Abstract: A stacked semiconductor device including a first substrate, a first insulating layer located on the first substrate, a second insulating layer located on the first insulating layer, a second substrate located on the second insulating layer, an external connection via extending through the second substrate in a first direction perpendicular to an upper surface of the second substrate and exposing an external connection pad, the external connection pad being located in the first insulating layer or the second insulating layer, and a protective ring formed in the second insulating layer and arranged to at least partially surround a sidewall of the external connection via with the first direction as an axial direction, but not to be exposed from the sidewall of the external connection via.

Abstract: An image sensor comprising a semiconductor substrate and a trench isolation structure that is formed in the semiconductor substrate, wherein the trench isolation structure sequentially includes, from an outer portion to an inner portion of the trench isolation structure, a first oxide layer, a nitride layer, a second oxide layer and a semiconductor material layer that respectively extend in a thickness direction of the semiconductor substrate, such that a semiconductor-oxide-nitride-oxide-semiconductor structure is formed from the semiconductor substrate to the inner portion of the trench isolation structure via the outer portion of the trench isolation structure.

Abstract: A stacked TSV structure comprises: a logic region in which a first metal wiring layer is formed, a pixel region located on the logic region, in which a second metal wiring layer is formed, and a through-silicon via including a first via penetrating from the first metal wiring layer upward through the logic region to the second metal wiring layer, wherein a contact is filled and formed in the through-silicon via, the contact contacting the first metal wiring layer and the second metal wiring layer, thereby electrically connecting the first metal wiring layer to the second metal wiring layer.

Abstract: The disclosure discloses a method of forming a double-layer color filter device and the structure of the color filter in an image sensor. The method includes: providing a photosensitive unit on a substrate; forming a first color filter layer on the photosensitive unit; etching the first color filter layer, to form a first filter having a first convex contour; and forming a second color filter layer on the first convex contour of the first filter, and etching the second color filter layer, to form a second filter having a second convex contour.

Abstract: A method of manufacturing a semiconductor device comprises: providing a stacked structure comprising a first wafer that includes a first substrate, a first insulating layer and a first electrical connector and a second wafer that includes a second substrate, a second insulating layer and a second electrical connector; forming a first portion of a TSV which overlaps at least part of the first and second electrical connectors and exposes a part of a surface of the first insulating layer; forming an insulating film that at least covers side surfaces and a bottom surface of the first portion; forming a first conductive barrier film retained on the side surfaces of the first portion; forming a second portion of the TSV that exposes the first and second electrical connectors; forming a conductive plug in the first and second portions, to interconnect the first and second electrical connectors.

Abstract: A semiconductor device comprises an array of photosensitive elements and a grid. The grid is arranged on the array of photosensitive elements, defines an opening for receiving light respectively for each photosensitive element, and optically isolates each photosensitive element from its adjacent photosensitive elements. The grid may comprise an optical isolation portion and a dielectric portion above the optical isolation portion, wherein the dielectric portion defines a sidewall tilted at an angle toward an outer side of the opening. Methods of manufacturing semiconductor devices are also disclosed.

Abstract: The method of manufacturing a semiconductor device, including preparing a semiconductor substrate, forming a first insulating layer over said semiconductor substrate, forming first grooves in the first insulating film, forming a gate electrode and a first interconnect in the first grooves, respectively, forming a gate insulating film over the gate electrode, forming a semiconductor layer over the gate insulating, forming a second insulating layer over the semiconductor layer and the first insulating film, forming a via in the second insulating layer, and forming a second interconnect such that the second interconnect is connected to the semiconductor layer through the via. The gate electrode, the first interconnect and the second interconnect are formed by Cu or Cu alloy, respectively.

Abstract: Provided is an in-wiring-layer active element (component) which allows for electrical isolation between a gate electrode and a channel in a top gate structure. A semiconductor device includes a first wiring layer, a second wiring layer, and a semiconductor element. The first wiring layer has a first interlayer insulating layer, and a first wire embedded in the first interlayer insulating layer. The second wiring layer has a second interlayer insulating layer, and second wires embedded in the second interlayer insulating layer. The semiconductor element is provided at least in the second wiring layer. The semiconductor element includes a semiconductor layer provided in the second wiring layer, a gate insulating film provided in contact with the semiconductor layer, a gate electrode provided on the opposite side of the semiconductor layer via the first gate insulating film, and a first side wall film provided over a side surface of the semiconductor layer.

Abstract: A semiconductor device includes a semiconductor substrate on which a semiconductor device is formed; first and second pads; a first insulating film which is formed above the semiconductor substrate; a plurality of wiring lines which are embedded in ditches provided in the first insulating film; a second insulating film provided to cover the first insulating film and the plurality of wiring lines; a semiconductor layer formed on the second insulating film; a source electrode connected with the semiconductor layer; and a drain electrode connected with the semiconductor layer. The plurality of wiring lines includes a gate electrode provided in a position which is opposite to the semiconductor layer. The semiconductor layer, the source electrode, the drain electrode and the gate electrode configure an ESD protection device to discharge a current by ESD surge from the first pad to the second pad.

Abstract: A circuit including an inverter is provided for a wiring layer. A semiconductor device is provided with a wiring layer circuit which is formed over an insulating film and includes at least one inverter element. The inverter is provided with a first transistor element and a resistance element which is connected to the first transistor via a connection node. The first transistor element is provided with a gate electrode which is embedded in an interlayer insulating film including the insulating film, a gate insulating film which is formed over the interlayer insulating film and the gate electrode, and a first semiconductor layer which is formed over the gate insulating film between a source electrode and a drain electrode. The resistance element is provided with a second semiconductor layer which functions as a resistance. The first semiconductor layer and the second semiconductor layer are formed in the same layer.

Abstract: The present invention makes it possible to lower the on resistance of a semiconductor element without hindering the function of a diffusion prevention film in a semiconductor device having the semiconductor element that uses a wire in a wiring layer as a gate electrode and has a gate insulation film in an identical layer to the diffusion prevention film. A first wire and a gate electrode are embedded into the surface layer of an insulation layer comprising a first wiring layer. A diffusion prevention film is formed between the first wiring layer and a second wiring layer. A gate insulation film is formed by: forming a recess over the upper face of the diffusion prevention film in the region overlapping with the gate electrode and around the region; and thinning the part.

Abstract: A semiconductor device has a p-type metal oxide semiconductor layer; a source electrode connected with the p-type metal oxide semiconductor layer; a drain electrode connected with the p-type metal oxide semiconductor layer; and a gate electrode arranged to oppose to a part of the p-type metal oxide semiconductor layer. The gate electrode and the drain electrode are separated from each other in a top view.

Abstract: The method of manufacturing a semiconductor device, including preparing a semiconductor substrate, forming a first insulating layer over said semiconductor substrate, forming first grooves in the first insulating film, forming a gate electrode and a first interconnect in the first grooves, respectively, forming a gate insulating film over the gate electrode, forming a semiconductor layer over the gate insulating, forming a second insulating layer over the semiconductor layer and the first insulating film, forming a via in the second insulating layer, and forming a second interconnect such that the second interconnect is connected to the semiconductor layer through the via. The gate electrode, the first interconnect and the second interconnect are formed by Cu or Cu alloy, respectively.

Abstract: Provided is an in-wiring-layer active element (component) which allows for electrical isolation between a gate electrode and a channel in a top gate structure. A semiconductor device includes a first wiring layer, a second wiring layer, and a semiconductor element. The first wiring layer has a first interlayer insulating layer, and a first wire embedded in the first interlayer insulating layer. The second wiring layer has a second interlayer insulating layer, and second wires embedded in the second interlayer insulating layer. The semiconductor element is provided at least in the second wiring layer. The semiconductor element includes a semiconductor layer provided in the second wiring layer, a gate insulating film provided in contact with the semiconductor layer, a gate electrode provided on the opposite side of the semiconductor layer via the first gate insulating film, and a first side wall film provided over a side surface of the semiconductor layer.

Abstract: A semiconductor device includes a semiconductor substrate on which a semiconductor device is formed; first and second pads; a first insulating film which is formed above the semiconductor substrate; a plurality of wiring lines which are embedded in ditches provided in the first insulating film; a second insulating film provided to cover the first insulating film and the plurality of wiring lines; a semiconductor layer formed on the second insulating film; a source electrode connected with the semiconductor layer; and a drain electrode connected with the semiconductor layer. The plurality of wiring lines includes a gate electrode provided in a position which is opposite to the semiconductor layer. The semiconductor layer, the source electrode, the drain electrode and the gate electrode configure an ESD protection device to discharge a current by ESD surge from the first pad to the second pad.

Abstract: The performances of semiconductor elements disposed in a multilayer wiring layer are improved. A semiconductor device includes: a first wire disposed in a first wiring layer; a second wire disposed in a second wiring layer stacked over the first wiring layer; a gate electrode arranged between the first wire and the second wire in the direction of stacking of the first wiring layer and the second wiring layer, and not coupled with the first wire and the second wire; a gate insulation film disposed over the side surface of the gate electrode; and a semiconductor layer disposed over the side surface of the gate electrode via the gate insulation film, and coupled with the first wire and the second wire.

Abstract: An interlayer insulating film is formed. Then a first gate electrode and a second gate electrode are buried in the interlayer insulating film. Then, an anti-diffusion film is formed over the interlayer insulating film, over the first gate electrode, and over the second gate electrode. Then, a first semiconductor layer is formed over the anti-diffusion film which is present over the first gate electrode. Then, an insulating cover film is formed over the upper surface and on the lateral side of the first semiconductor layer and over the anti-diffusion film. Then, a semiconductor film is formed over the insulating cover film. Then, the semiconductor film is removed selectively to leave a portion positioned over the second gate electrode, thereby forming a second semiconductor layer.

Abstract: A semiconductor device has a p-type metal oxide semiconductor layer; a source electrode connected with the p-type metal oxide semiconductor layer; a drain electrode connected with the p-type metal oxide semiconductor layer; and a gate electrode arranged to oppose to a part of the p-type metal oxide semiconductor layer. The gate electrode and the drain electrode are separated from each other in a top view.

Abstract: A semiconductor device is provided which includes an N-type semiconductor layer and a P-type semiconductor layer coexisting in the same wiring layer without influences on the properties of a semiconductor layer. The semiconductor device includes a first wiring layer with a first wiring, a second wiring layer with a second wiring, and first and second transistors provided in the first and second wiring layers. The first transistor includes a first gate electrode, a first gate insulating film, a first oxide semiconductor layer, a first hard mask layer, and first insulating sidewall films covering the sides of the first oxide semiconductor layer. The second transistor includes a second gate electrode, a second gate insulating film, a second oxide semiconductor layer, and a second hard mask layer.

Abstract: The present invention makes it possible to lower the on resistance of a semiconductor element without hindering the function of a diffusion prevention film in a semiconductor device having the semiconductor element that uses a wire in a wiring layer as a gate electrode and has a gate insulation film in an identical layer to the diffusion prevention film. A first wire and a gate electrode are embedded into the surface layer of an insulation layer comprising a first wiring layer. A diffusion prevention film is formed between the first wiring layer and a second wiring layer. A gate insulation film is formed by: forming a recess over the upper face of the diffusion prevention film in the region overlapping with the gate electrode and around the region; and thinning the part.