Abstract: A first pseudo random number generating circuit sequentially provides an output signal to a matching detecting circuit in response to a clock signal. A second pseudo random number generating circuit generates an initial value, and then, sequentially provides an output signal to a storage device in response to an output signal from the matching detecting circuit and the clock signal. Data with the output signal as an address is provided as an output signal from the storage device. When the matching detecting circuit detects matching between the output signals, the matching detecting circuit provides the output signals to the second pseudo random number generating circuit and an AND logic circuit. As described above, when the output signal of the matching detecting circuit is provided, the output signals from the storage device are provided as respective output control signals.

Abstract: A vector operation data path (3) in a vector calculator is composed of a cumulative data selection unit (5) and a cumulative calculator (6). The cumulative data selection unit (5) outputs cumulative data Z(1) to Z(n) which are time series data on the basis of operation data A and operation data Y, sequentially to the cumulative calculator (6). A selector (66) in the cumulative calculator (6) outputs selected data S(i) by selecting one of differential data {Z(i)-Z(i+1)}, differential data {Z(i)-Z(i+2)} and cumulative data Z(i). The selected data S(i) is applied to an absolute value circuit (67) and a square circuit (68), and the obtained square data SQ(i) is given to an accumulator (69), and the accumulator (69) determines the cumulative value.

Abstract: A selecting circuit is formed of two tristate gates. The size of each of a plurality of transistors configuring a tristate gate processing a signal having a shorter delay time is set smaller than the size of each of a plurality of transistors configuring a tristate gate processing a signal having a longer delay time, so that the capacitance of the former transistors is decreased. As a result, the load to be driven by each of transistors to which a signal having a longer delay time is applied is decreased, whereby the entire circuit can be increased in operation speed. Accordingly, the selecting circuit selecting between two or more input signals having different delay times can operate at a high speed.

Abstract: The semiconductor test system comprises an OBIC measuring device (8) and a tester (5). The tester (5) transmits a test signal to an input pad (2a) of a semiconductor integrated circuit (1). In synchronization with this, the OBIC measuring device (8) irradiates drain regions (6) of the semiconductor integrated circuit (1) with a laser beam (7) one after another, to thereby detect the generation of the OBIC. An comparator (5c) in the tester (5) compares an output signal from an output pad (2b) of the semiconductor integrated circuit (1) and an OBIC detection signal from the OBIC measuring device (8) with expected values (5b).