Abstract: A semiconductor storage device includes a first semiconductor substrate, a second semiconductor substrate, a first memory cell and a second memory cell provided between the first semiconductor substrate and the second semiconductor substrate, a first word line electrically connected to the first memory cell, a second word line electrically connected to the second memory cell, a first transistor that is provided on the first semiconductor substrate and electrically connected between the first word line and a first wiring through which a voltage is applied to the first word line, and a second transistor that is provided on the semiconductor substrate and electrically connected between the second word line and a second wiring through which a voltage is applied to the second word line.

Abstract: A semiconductor storage device includes a first semiconductor substrate, a second semiconductor substrate, a first memory cell and a second memory cell provided between the first semiconductor substrate and the second semiconductor substrate, a first word line electrically connected to the first memory cell, a second word line electrically connected to the second memory cell, a first transistor that is provided on the first semiconductor substrate and electrically connected between the first word line and a first wiring through which a voltage is applied to the first word line, and a second transistor that is provided on the semiconductor substrate and electrically connected between the second word line and a second wiring through which a voltage is applied to the second word line.

Abstract: A semiconductor storage device of an embodiment includes a wiring layer M1 and a wiring layer M2. The wiring layer M1 includes a signal line through which a data signal is transferred, and a plurality of dummy patterns formed of a material same as a material of the signal line. The wiring layer M2 includes a voltage supply line through which voltage Vdd is supplied and another voltage supply line through which voltage Vss is supplied. Each of the dummy patterns is electrically connected with any one of the voltage supply lines. In a dummy pattern disposed adjacent to the signal line, a surface facing the signal line is constituted by a first surface positioned at a first distance to the signal line and a second surface positioned at a second distance to the signal line, the second distance being different from the first distance.

Abstract: A semiconductor storage device includes a first semiconductor substrate, a second semiconductor substrate, a first memory cell and a second memory cell provided between the first semiconductor substrate and the second semiconductor substrate, a first word line electrically connected to the first memory cell, a second word line electrically connected to the second memory cell, a first transistor that is provided on the first semiconductor substrate and electrically connected between the first word line and a first wiring through which a voltage is applied to the first word line, and a second transistor that is provided on the semiconductor substrate and electrically connected between the second word line and a second wiring through which a voltage is applied to the second word line.

Abstract: A semiconductor storage device of an embodiment includes a wiring layer M1 and a wiring layer M2. The wiring layer M1 includes a signal line through which a data signal is transferred, and a plurality of dummy patterns formed of a material same as a material of the signal line. The wiring layer M2 includes a voltage supply line through which voltage Vdd is supplied and another voltage supply line through which voltage Vss is supplied. Each of the dummy patterns is electrically connected with any one of the voltage supply lines. In a dummy pattern disposed adjacent to the signal line, a surface facing the signal line is constituted by a first surface positioned at a first distance to the signal line and a second surface positioned at a second distance to the signal line, the second distance being different from the first distance.

Abstract: A semiconductor storage device includes first high-potential wirings, second high-potential wirings, a first low-potential wiring, a second low-potential wiring, a first branch wiring, and a second branch wiring formed in a wiring layer between a memory cell array and a semiconductor substrate and each extending in a first direction. The first branch wiring is electrically connected to the first low-potential wiring, and is adjacent to the first low-potential wiring on one side in a second direction perpendicular to the first direction of the first low-potential wiring. The second branch wiring is electrically connected to the second low-potential wiring, and is adjacent to the second low-potential wiring on the other side in the second direction of the second low-potential wiring. A first via is provided to contact the first branch wiring, and a second via is provided to contact the second branch wiring.

Abstract: A semiconductor storage device includes first high-potential wirings, second high-potential wirings, a first low-potential wiring, a second low-potential wiring, a first branch wiring, and a second branch wiring formed in a wiring layer between a memory cell array and a semiconductor substrate and each extending in a first direction. The first branch wiring is electrically connected to the first low-potential wiring, and is adjacent to the first low-potential wiring on one side in a second direction perpendicular to the first direction of the first low-potential wiring. The second branch wiring is electrically connected to the second low-potential wiring, and is adjacent to the second low-potential wiring on the other side in the second direction of the second low-potential wiring. A first via is provided to contact the first branch wiring, and a second via is provided to contact the second branch wiring.

Abstract: This nonvolatile semiconductor memory device comprises: a memory cell array configured having a plurality of blocks arranged therein, each of the blocks configured as an arrangement of NAND cell units, each of the NAND cell units configured having a plurality of electrically rewritable memory cells and a select transistor connected in series; and a row decoder configured to select anyone of the blocks of the memory cell array and supply to any one of said blocks a voltage required in various kinds of operations. The row decoder comprises: a plurality of first transfer transistors each disposed in a first region and connected to any one of the memory cells; and a plurality of second transfer transistors each disposed in a second region and connected to the select transistor, the second region being a residual region of the first region.

Abstract: This nonvolatile semiconductor memory device comprises: a memory cell array configured having a plurality of blocks arranged therein, each of the blocks configured as an arrangement of NAND cell units, each of the NAND cell units configured having a plurality of electrically rewritable memory cells and a select transistor connected in series; and a row decoder configured to select anyone of the blocks of the memory cell array and supply to any one of said blocks a voltage required in various kinds of operations. The row decoder comprises: a plurality of first transfer transistors each disposed in a first region and connected to any one of the memory cells; and a plurality of second transfer transistors each disposed in a second region and connected to the select transistor, the second region being a residual region of the first region.

Abstract: A method of controlling a programming of a flash memory with memory blocks. The method includes checking whether a selected block among the memory blocks belongs to a first group or a second group. The method further includes executing the programming from a least bit address when the selected block belongs to the first group. The method also includes executing the programming from a most bit address when the selected block belongs to the second group.

Abstract: A method of controlling a programming of a flash memory with memory blocks. The method includes checking whether a selected block among the memory blocks belongs to a first group or a second group. The method further includes executing the programming from a least bit address when the selected block belongs to the first group. The method also includes executing the programming from a most bit address when the selected block belongs to the second group.

Abstract: A NAND flash memory according to examples of the invention includes a memory cell array comprised of first, second, and third NAND blocks disposed in order in a first direction and first and second transfer transistor blocks disposed in order in the first direction at one end in a second direction intersecting with the first direction of the memory cell array. An address allocation to the word lines in the first NAND block is inverted against an address allocation to the word lines in the third NAND block.

Abstract: A NAND flash memory according to examples of the invention includes a memory cell array comprised of first, second, and third NAND blocks disposed in order in a first direction and first and second transfer transistor blocks disposed in order in the first direction at one end in a second direction intersecting with the first direction of the memory cell array. An address allocation to the word lines in the first NAND block is inverted against an address allocation to the word lines in the third NAND block.

Abstract: An ASIC includes a first-wire extended in a first-direction and a second-wire extended in a parallel direction to the first-wire and both are placed on a first-wire layer; and a third-wire placed on a second-wire layer above the first-wire layer and is extended above the wire and above the second-wire in a second-direction which intersects the first-direction and passing through a first via-hole is connected to the first-wire, and a fourth-wire separated from the third-wire extended in a parallel direction above the first-wire and above the second-wire and a fifth-wire separated from both the third-wire and the fourth-wire and extended in a parallel direction in a smallest space and passing through a second via-hole is connected to the second-wire, wherein, one end of the fifth-wire is extended to the center between the second-wire and the first-wire from above the second-wire.

Abstract: An ASIC includes a first-wire extended in a first-direction and a second-wire extended in a parallel direction to the first-wire and both are placed on a first-wire layer; and a third-wire placed on a second-wire layer above the first-wire layer and is extended above the wire and above the second-wire in a second-direction which intersects the first-direction and passing through a first via-hole is connected to the first-wire, and a fourth-wire separated from the third-wire extended in a parallel direction above the first-wire and above the second-wire and a fifth-wire separated from both the third-wire and the fourth-wire and extended in a parallel direction in a smallest space and passing through a second via-hole is connected to the second-wire, wherein, one end of the fifth-wire is extended to the center between the second-wire and the first-wire from above the second-wire.

Abstract: A non-volatile semiconductor memory includes: a cell array including a plurality of memory cells arranged in a matrix; a plurality of bit lines extending in a column direction of the matrix; a sense amplifier configured to amplify data read out from the memory cells via the bit lines; a shield power supply providing a voltage to shield the bit lines; and a bit line selection circuit, configured to connect even bit lines to the shield power supply when odd bit lines are connected to the sense amplifier, and to connect the odd bit lines to the shield power supply when the even bit lines are connected to the sense amplifier.

Abstract: A non-volatile semiconductor memory includes: a cell array including a plurality of memory cells arranged in a matrix; a plurality of bit lines extending in a column direction of the matrix; a sense amplifier configured to amplify data read out from the memory cells via the bit lines; a shield power supply providing a voltage to shield the bit lines; and a bit line selection circuit, configured to connect even bit lines to the shield power supply when odd bit lines are connected to the sense amplifier, and to connect the odd bit lines to the shield power supply when the even bit lines are connected to the sense amplifier.

Abstract: A p-well region (16) is formed in the main surface area of an n-type semiconductor substrate (11). A potential (V.sub.BB) which is lower than an externally input potential is applied to the p-well region (16). In the surface area of the p-well region (16), a first impurity diffused layer (12) of n-type to which the externally input potential (Vin) is applied and a second impurity diffused layer (13) of n-type to which a reference potential is applied are formed. The first impurity diffused layer (12) serves as the drain region of a first MOS transistor (Q9) of n-channel formed in the p-well region (16) and the second impurity diffused layer (13) serves as the drain region of a second MOS transistor (Q10) of n-channel which is also formed in the p-well region (16). The first and second MOS transistors (Q9 and Q10) constitute the input section of an input circuit.

Abstract: In a dynamic type memory, a memory cell array is divided into a plurality of sub arrays on a memory chip. Each of the sub arrays is provided with a data line formed in parallel with word lines. Data buffer and multiplexer circuits and I/O pads are arranged on one side of the memory chip in parallel with bit lines. This arrangement allows a data path to be shortened and enables data to be transferred at high speed.

Abstract: In a dynamic type memory, a memory cell array is divided into a plurality of sub arrays on a memory chip. Each of the sub arrays is provided with a data line formed in parallel with word lines. Data buffer and multiplexer circuits and I/O pads are arranged on one side of the memory chip in parallel with bit lines. This arrangement allows a data path to be shortened and enables data to be transferred at high speed.