Patents by Inventor Kiyohiko Sakakibara
Kiyohiko Sakakibara has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11763907Abstract: Systems and methods for improving the reliability of non-volatile memory by reducing the number of memory cell transistors that experience excessive hole injection are described. The excessive hole injection may occur when the threshold voltage for a memory cell transistor is being set below a particular negative threshold voltage. To reduce the number of memory cell transistors with threshold voltages less than the particular negative threshold voltage, the programmed data states of the memory cell transistors may be reversed such that the erased state comprises the highest data state corresponding with the highest threshold voltage distribution. To facilitate programming of the memory cell transistors with reversed programmed data states, a non-volatile memory device structure may be used in which the bit line connections to NAND strings comprise direct poly-channel contact to P+ silicon and the source line connections to the NAND strings comprise direct poly-channel contact to N+ silicon.Type: GrantFiled: August 23, 2022Date of Patent: September 19, 2023Assignee: SanDisk Technologies LLCInventor: Kiyohiko Sakakibara
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Patent number: 11631691Abstract: A three-dimensional memory device includes alternating stacks of insulating strips and electrically conductive strips located over a substrate and laterally spaced apart among one another by line trenches which laterally extend along a first horizontal direction and are spaced apart along a second horizontal direction, and memory stack structures arranged in rows extending along the first horizontal direction. Each row of memory stack structures is located on a respective sidewall of the line trenches. Each of the memory stack structures includes a vertical semiconductor channel, a tunneling dielectric contacting the vertical semiconductor channel, a charge storage layer contacting the tunneling dielectric, and a composite blocking dielectric. The composite blocking dielectric includes a first dipole-containing blocking dielectric layer stack, a homogeneous blocking dielectric layer, and a second dipole-containing blocking dielectric layer stack.Type: GrantFiled: May 18, 2020Date of Patent: April 18, 2023Assignee: SANDISK TECHNOLOGIES LLCInventors: Masatoshi Nishikawa, Kiyohiko Sakakibara
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Publication number: 20220406390Abstract: Systems and methods for improving the reliability of non-volatile memory by reducing the number of memory cell transistors that experience excessive hole injection are described. The excessive hole injection may occur when the threshold voltage for a memory cell transistor is being set below a particular negative threshold voltage. To reduce the number of memory cell transistors with threshold voltages less than the particular negative threshold voltage, the programmed data states of the memory cell transistors may be reversed such that the erased state comprises the highest data state corresponding with the highest threshold voltage distribution. To facilitate programming of the memory cell transistors with reversed programmed data states, a non-volatile memory device structure may be used in which the bit line connections to NAND strings comprise direct poly-channel contact to P+ silicon and the source line connections to the NAND strings comprise direct poly-channel contact to N+ silicon.Type: ApplicationFiled: August 23, 2022Publication date: December 22, 2022Applicant: SANDISK TECHNOLOGIES LLCInventor: Kiyohiko Sakakibara
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Patent number: 11456044Abstract: Systems and methods for improving the reliability of non-volatile memory by reducing the number of memory cell transistors that experience excessive hole injection are described. The excessive hole injection may occur when the threshold voltage for a memory cell transistor is being set below a particular negative threshold voltage. To reduce the number of memory cell transistors with threshold voltages less than the particular negative threshold voltage, the programmed data states of the memory cell transistors may be reversed such that the erased state comprises the highest data state corresponding with the highest threshold voltage distribution. To facilitate programming of the memory cell transistors with reversed programmed data states, a non-volatile memory device structure may be used in which the bit line connections to NAND strings comprise direct poly-channel contact to P+ silicon and the source line connections to the NAND strings comprise direct poly-channel contact to N+ silicon.Type: GrantFiled: March 11, 2021Date of Patent: September 27, 2022Assignee: SanDisk Technologies LLCInventor: Kiyohiko Sakakibara
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Publication number: 20220293198Abstract: Systems and methods for improving the reliability of non-volatile memory by reducing the number of memory cell transistors that experience excessive hole injection are described. The excessive hole injection may occur when the threshold voltage for a memory cell transistor is being set below a particular negative threshold voltage. To reduce the number of memory cell transistors with threshold voltages less than the particular negative threshold voltage, the programmed data states of the memory cell transistors may be reversed such that the erased state comprises the highest data state corresponding with the highest threshold voltage distribution. To facilitate programming of the memory cell transistors with reversed programmed data states, a non-volatile memory device structure may be used in which the bit line connections to NAND strings comprise direct poly-channel contact to P+ silicon and the source line connections to the NAND strings comprise direct poly-channel contact to N+ silicon.Type: ApplicationFiled: March 11, 2021Publication date: September 15, 2022Applicant: SANDISK TECHNOLOGIES LLCInventor: Kiyohiko Sakakibara
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Publication number: 20220254382Abstract: A non-volatile memory device is provided that includes an alternating stack of conducting layers and dielectric layers, a charge trap layer, a layer of polysilicon, and a tunneling dielectric layer arranged between the charge trap layer and the layer of polysilicon. The charge trap layer extends through the alternating stack of conducting layers and dielectric layers. The layer of polysilicon includes a first portion having a first thickness and a second portion having a second thickness that is greater than the first thickness. The second portion is arranged below the alternating stack of conducting layers and dielectric layers.Type: ApplicationFiled: April 28, 2022Publication date: August 11, 2022Applicant: SanDisk Technologies LLCInventors: Kiyohiko Sakakibara, Ken Oowada
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Patent number: 11348649Abstract: Methods for reducing read disturb using NAND strings with poly-silicon channels and p-type doped source lines are described. During a boosted read operation for a selected memory cell transistor in a NAND string, a back-gate bias or bit line voltage may be applied to a bit line connected to the NAND string and a source line voltage greater than the bit line voltage may be applied to a source line connected to the NAND string; with these bias conditions, electrons may be injected from the bit line and annihilated in the source line during the read operation. To avoid leakage currents through NAND strings in non-selected memory blocks, the threshold voltages of source-side select gate transistors of the NAND strings may be set to a negative threshold voltage that has an absolute voltage value greater than the source line voltage applied during the read operation.Type: GrantFiled: June 23, 2020Date of Patent: May 31, 2022Assignee: SanDisk Technologies LLCInventors: Kiyohiko Sakakibara, Hiroki Yabe, Ken Oowada, Masaaki Higashitani
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Patent number: 11342006Abstract: Methods for reducing manufacturing cost and improving the reliability of non-volatile memories using NAND strings with polysilicon channels and p-type doped source lines are described. A NAND string may include a polysilicon channel that is orthogonal to a substrate and connects to a boron doped source line at a source-side end of the NAND string. To reduce the likelihood of the polysilicon channel being cut-off or pinched near the source-side end of the NAND string, a thicker polysilicon channel may be formed near the source-side end of the NAND string while a thinner polysilicon channel may be formed for the remainder of the NAND string by diffusing boron into a first portion of the polysilicon channel corresponding with the thicker polysilicon channel and then etching the polysilicon channel with etchants that exhibit a reduction in their etch rate at a boron concentration above a threshold concentration.Type: GrantFiled: October 28, 2019Date of Patent: May 24, 2022Assignee: SanDisk Technologies LLCInventors: Kiyohiko Sakakibara, Ken Oowada
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Patent number: 11227663Abstract: Methods for reducing read disturb using NAND strings with poly-silicon channels and p-type doped source lines are described. During a boosted read operation for a selected memory cell transistor in a NAND string, a back-gate bias or bit line voltage may be applied to a bit line connected to the NAND string and a source line voltage greater than the bit line voltage may be applied to a source line connected to the NAND string; with these bias conditions, electrons may be injected from the bit line and annihilated in the source line during the read operation. To avoid leakage currents through NAND strings in non-selected memory blocks, the threshold voltages of source-side select gate transistors of the NAND strings may be set to a negative threshold voltage that has an absolute voltage value greater than the source line voltage applied during the read operation.Type: GrantFiled: February 10, 2021Date of Patent: January 18, 2022Assignee: SanDisk Technologies LLCInventors: Kiyohiko Sakakibara, Ippei Yasuda, Ken Oowada, Masaaki Higashitani
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Publication number: 20210174881Abstract: Methods for reducing read disturb using NAND strings with poly-silicon channels and p-type doped source lines are described. During a boosted read operation for a selected memory cell transistor in a NAND string, a back-gate bias or bit line voltage may be applied to a bit line connected to the NAND string and a source line voltage greater than the bit line voltage may be applied to a source line connected to the NAND string; with these bias conditions, electrons may be injected from the bit line and annihilated in the source line during the read operation. To avoid leakage currents through NAND strings in non-selected memory blocks, the threshold voltages of source-side select gate transistors of the NAND strings may be set to a negative threshold voltage that has an absolute voltage value greater than the source line voltage applied during the read operation.Type: ApplicationFiled: February 10, 2021Publication date: June 10, 2021Applicant: SANDISK TECHNOLOGIES LLCInventors: Kiyohiko Sakakibara, Ippei Yasuda, Ken Oowada, Masaaki Higashitani
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Patent number: 11004518Abstract: Methods for reducing read disturb using NAND strings with poly-silicon channels and p-type doped source lines are described. During a boosted read operation for a selected memory cell transistor in a NAND string, a back-gate bias or bit line voltage may be applied to a bit line connected to the NAND string and a source line voltage greater than the bit line voltage may be applied to a source line connected to the NAND string; with these bias conditions, electrons may be injected from the bit line and annihilated in the source line during the read operation. To avoid leakage currents through NAND strings in non-selected memory blocks, the threshold voltages of source-side select gate transistors of the NAND strings may be set to a negative threshold voltage that has an absolute voltage value greater than the source line voltage applied during the read operation.Type: GrantFiled: June 28, 2019Date of Patent: May 11, 2021Assignee: SANDISK TECHNOLOGIES LLCInventors: Kiyohiko Sakakibara, Hiroki Yabe, Ken Oowada, Masaaki Higashitani
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Publication number: 20210125643Abstract: Methods for reducing manufacturing cost and improving the reliability of non-volatile memories using NAND strings with polysilicon channels and p-type doped source lines are described. A NAND string may include a polysilicon channel that is orthogonal to a substrate and connects to a boron doped source line at a source-side end of the NAND string. To reduce the likelihood of the polysilicon channel being cut-off or pinched near the source-side end of the NAND string, a thicker polysilicon channel may be formed near the source-side end of the NAND string while a thinner polysilicon channel may be formed for the remainder of the NAND string by diffusing boron into a first portion of the polysilicon channel corresponding with the thicker polysilicon channel and then etching the polysilicon channel with etchants that exhibit a reduction in their etch rate at a boron concentration above a threshold concentration.Type: ApplicationFiled: October 28, 2019Publication date: April 29, 2021Applicant: SanDisk Technologies LLCInventors: Kiyohiko Sakakibara, Ken Oowada
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Patent number: 10957401Abstract: Methods for reducing read disturb using NAND strings with poly-silicon channels and p-type doped source lines are described. During a boosted read operation for a selected memory cell transistor in a NAND string, a back-gate bias or bit line voltage may be applied to a bit line connected to the NAND string and a source line voltage greater than the bit line voltage may be applied to a source line connected to the NAND string; with these bias conditions, electrons may be injected from the bit line and annihilated in the source line during the read operation. To avoid leakage currents through NAND strings in non-selected memory blocks, the threshold voltages of source-side select gate transistors of the NAND strings may be set to a negative threshold voltage that has an absolute voltage value greater than the source line voltage applied during the read operation.Type: GrantFiled: June 23, 2020Date of Patent: March 23, 2021Assignee: SANDISK TECHNOLOGIES LLCInventors: Kiyohiko Sakakibara, Ippei Yasuda, Ken Oowada, Masaaki Higashitani
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Patent number: 10950311Abstract: Methods for reducing read disturb using NAND strings with poly-silicon channels and p-type doped source lines are described. During a boosted read operation for a selected memory cell transistor in a NAND string, a back-gate bias or bit line voltage may be applied to a bit line connected to the NAND string and a source line voltage greater than the bit line voltage may be applied to a source line connected to the NAND string; with these bias conditions, electrons may be injected from the bit line and annihilated in the source line during the read operation. To avoid leakage currents through NAND strings in non-selected memory blocks, the threshold voltages of source-side select gate transistors of the NAND strings may be set to a negative threshold voltage that has an absolute voltage value greater than the source line voltage applied during the read operation.Type: GrantFiled: June 28, 2019Date of Patent: March 16, 2021Assignee: SANDISK TECHNOLOGIES LLCInventors: Kiyohiko Sakakibara, Ippei Yasuda, Ken Oowada, Masaaki Higashitani
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Patent number: 10916556Abstract: A three-dimensional memory device includes a source-level material layer stack located over a substrate that includes, from bottom to top, a lower source-level semiconductor layer, a semiconductor oxide tunneling layer, a source contact layer including a doped semiconductor material, and an upper source-level semiconductor layer, an alternating stack of electrically conductive layers and insulating layers located over the source-level material layer stack, and memory stack structures that extend through the alternating stack and into an upper portion of the lower source-level semiconductor layer, in which each memory stack structure includes a vertical semiconductor channel and a memory film laterally surrounding the vertical semiconductor channel, and each of the vertical semiconductor channels vertically extends through, and is electrically connected to, the source contact layer.Type: GrantFiled: November 26, 2018Date of Patent: February 9, 2021Assignee: SANDISK TECHNOLOGIES LLCInventors: Kiyohiko Sakakibara, Takumi Moriyama, Yu-Hsien Hsu
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Patent number: 10903222Abstract: A three-dimensional memory device includes source-level material layers located over a substrate and including a lower semiconductor layer, a source contact layer, and an upper semiconductor layer. The lower semiconductor layer includes a first boron-doped semiconductor material, the upper semiconductor layer includes carbon doped second boron-doped semiconductor material, and the source contact layer includes a boron-doped semiconductor material. An alternating stack of insulating layers and electrically conductive layers is located over the source-level material layers. Memory stack structures vertically extend through the alternating stack, the upper semiconductor layer, and the source contact layer. Each of the memory stack structures includes a respective memory film and a respective vertical semiconductor channel that contacts the source contact layer.Type: GrantFiled: May 10, 2019Date of Patent: January 26, 2021Assignee: SANDISK TECHNOLOGIES LLCInventors: Kiyohiko Sakakibara, Masaaki Higashitani, Masanori Tsutsumi, Zhixin Cui
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Publication number: 20200411115Abstract: Methods for reducing read disturb using NAND strings with poly-silicon channels and p-type doped source lines are described. During a boosted read operation for a selected memory cell transistor in a NAND string, a back-gate bias or bit line voltage may be applied to a bit line connected to the NAND string and a source line voltage greater than the bit line voltage may be applied to a source line connected to the NAND string; with these bias conditions, electrons may be injected from the bit line and annihilated in the source line during the read operation. To avoid leakage currents through NAND strings in non-selected memory blocks, the threshold voltages of source-side select gate transistors of the NAND strings may be set to a negative threshold voltage that has an absolute voltage value greater than the source line voltage applied during the read operation.Type: ApplicationFiled: June 23, 2020Publication date: December 31, 2020Applicant: SANDISK TECHNOLOGIES LLCInventors: Kiyohiko Sakakibara, Ippei Yasuda, Ken Oowada, Masaaki Higashitani
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Publication number: 20200411113Abstract: Methods for reducing read disturb using NAND strings with poly-silicon channels and p-type doped source lines are described. During a boosted read operation for a selected memory cell transistor in a NAND string, a back-gate bias or bit line voltage may be applied to a bit line connected to the NAND string and a source line voltage greater than the bit line voltage may be applied to a source line connected to the NAND string; with these bias conditions, electrons may be injected from the bit line and annihilated in the source line during the read operation. To avoid leakage currents through NAND strings in non-selected memory blocks, the threshold voltages of source-side select gate transistors of the NAND strings may be set to a negative threshold voltage that has an absolute voltage value greater than the source line voltage applied during the read operation.Type: ApplicationFiled: June 28, 2019Publication date: December 31, 2020Applicant: SANDISK TECHNOLOGIES LLCInventors: Kiyohiko Sakakibara, Hiroki Yabe, Ken Oowada, Masaaki Higashitani
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Publication number: 20200411114Abstract: Methods for reducing read disturb using NAND strings with poly-silicon channels and p-type doped source lines are described. During a boosted read operation for a selected memory cell transistor in a NAND string, a back-gate bias or bit line voltage may be applied to a bit line connected to the NAND string and a source line voltage greater than the bit line voltage may be applied to a source line connected to the NAND string; with these bias conditions, electrons may be injected from the bit line and annihilated in the source line during the read operation. To avoid leakage currents through NAND strings in non-selected memory blocks, the threshold voltages of source-side select gate transistors of the NAND strings may be set to a negative threshold voltage that has an absolute voltage value greater than the source line voltage applied during the read operation.Type: ApplicationFiled: June 23, 2020Publication date: December 31, 2020Applicant: SANDISK TECHNOLOGIES LLCInventors: Kiyohiko Sakakibara, Hiroki Yabe, Ken Oowada, Masaaki Higashitani
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Publication number: 20200411112Abstract: Methods for reducing read disturb using NAND strings with poly-silicon channels and p-type doped source lines are described. During a boosted read operation for a selected memory cell transistor in a NAND string, a back-gate bias or bit line voltage may be applied to a bit line connected to the NAND string and a source line voltage greater than the bit line voltage may be applied to a source line connected to the NAND string; with these bias conditions, electrons may be injected from the bit line and annihilated in the source line during the read operation. To avoid leakage currents through NAND strings in non-selected memory blocks, the threshold voltages of source-side select gate transistors of the NAND strings may be set to a negative threshold voltage that has an absolute voltage value greater than the source line voltage applied during the read operation.Type: ApplicationFiled: June 28, 2019Publication date: December 31, 2020Applicant: SANDISK TECHNOLOGIES LLCInventors: Kiyohiko Sakakibara, Ippei Yasuda, Ken Oowada, Masaaki Higashitani