Abstract: The present invention provides an image processing unit, an image processing system, and an image processing method capable of achieving a higher speed and a higher efficiency in a rendering and implementing a low cost of the system. The image processing unit according to the present invention comprises a main storing portion for storing information of three-dimensional objects, a plurality of calculating portions for processing images based on three-dimensional object information which are read from the main storing portion, and a hierarchical storing portion having a plurality of hierarchies and connected between the main storing portion and the plurality of calculating portions to store a part of information at a lower level into a higher level sequentially, wherein image processing by the plurality of calculating portions are performed in parallel.

Abstract: The present invention provides an image processing unit, an image processing system, and an image processing method capable of achieving a higher speed and a higher efficiency in a rendering and implementing a low cost of the system. The image processing unit according to the present invention comprises a main storing portion for storing information of three-dimensional objects, a plurality of calculating portions for processing images based on three-dimensional object information which are read from the main storing portion, and a hierarchical storing portion having a plurality of hierarchies and connected between the main storing portion and the plurality of calculating portions to store a part of information at a lower level into a higher level sequentially, wherein image processing by the plurality of calculating portions are performed in parallel.

Abstract: The present invention provides an image processing unit, an image processing system, and an image processing method capable of achieving a higher speed and a higher efficiency in a rendering and implementing a low cost of the system. The image processing unit according to the present invention comprises a main storing portion for storing information of three-dimensional objects, a plurality of calculating portions for processing images based on three-dimensional object information which are read from the main storing portion, and a hierarchical storing portion having a plurality of hierarchies and connected between the main storing portion and the plurality of calculating portions to store a part of information at a lower level into a higher level sequentially, wherein image processing by the plurality of calculating portions are performed in parallel.

Abstract: In a memory composed of a plurality of banks, even if succeeding access is performed to the same bank as that being currently accessed, the succeeding access can be controlled according to the destination which is currently accessed and its accessed state. In addition, if particular relationships exist between a precedingly accessed destination and the succeedingly accessed destination, a corresponding main word line out of main word lines which correspond to respective rows of respective banks can be still held in its selected state even after the preceding access has been terminated.

Abstract: A delay time measuring circuit includes a delay circuit for changing the delay times of first and second clock signals output to measure the delay time of an evaluated circuit according to an externally supplied control voltage, and a voltage controlled oscillator whose oscillation frequency is controlled by the same control voltage as that used for the delay circuit, and is constructed to measure the delay time of the evaluated circuit based on an output of the voltage controlled oscillator. Therefore, it is possible to precisely evaluate the operation speed of a circuit operating at high speed.

Abstract: An instruction cache unit output four instructions, each constituted by 32 bits, which are input to an instruction supplier. The instruction supplier distributes the four instructions to five. The five instructions are selectively supplied to two integer/logical arithmetic processor unit, two floating-point arithmetic processor unit, and a branch processor unit.

Abstract: A multiport memory device according to this invention comprises a power source, a memory cell for storing data, a first bit line, a first word line, a first switch which has an input section connected to the first word line and a current path whose one end is connected to the first bit line, and which provides on/off control according to the potential of the first word line, a second bit line, a second word line, a second switch which has an input section connected to the second word line and a current path whose one end is connected to the second bit line, and which provides on/off control according to the potential of the second word line.