Patents by Inventor Kiyokazu Nishioka
Kiyokazu Nishioka has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7457890Abstract: An integrated multimedia system having a multimedia processor is disposed in an integrated circuit having a first host processor system coupled to the multimedia processor and a second local processor disposed within the multimedia processor for controlling the operation of the multimedia processor. A data transfer switch is coupled to the second processor for transferring data to various modules of the processor, at least one of which is a data cache. The data transfer switch transfers data in either direction between the cache and a module within the processor. A data streamer schedules simultaneous data transfers among the various-modules disposed within the multimedia processor in accordance with corresponding channel allocations. An interface unit is coupled to the data streamer and has a plurality of input/output (I/O) device driver units. A plurality of external I/O devices are coupled to the plurality of I/O device driver units via a multiplexer.Type: GrantFiled: October 30, 2006Date of Patent: November 25, 2008Assignee: Hitachi, Ltd.Inventors: David Baker, Christopher Basoglu, Benjamin Cutler, Richard Deeley, Gregorio Gervasio, Atsuo Kawaguchi, Keiji Kojima, Woobin Lee, Takeshi Miyazaki, Yatin Mundkur, Vinay Naik, Kiyokazu Nishioka, Toru Nojiri, John O'Donnell, Sarang Padalkar
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Patent number: 7272670Abstract: An integrated multimedia system has a multimedia processor disposed in an integrated circuit. A processor is disposed within the multimedia processor which controls the operation of the multimedia processor. A data transfer switch is disposed within the multimedia processor and coupled to the processor which transfers data to various modules of the multimedia processor. A fixed function unit is disposed within the multimedia processor, coupled to the processor and the data transfer switch. A data streamer is coupled to the data transfer switch, and configured to schedule simultaneous data transfers among a plurality of modules disposed within the multimedia processor in accordance with the corresponding channel allocations. As interface unit is coupled to the data streamer and has a plurality of I/O device driver units. A multiplexer coupled to the interface unit provides access between a selected number of I/O device driver units and external I/O devices via output pins.Type: GrantFiled: February 5, 2001Date of Patent: September 18, 2007Assignee: HitachiInventors: David Baker, Christopher Basoglu, Benjamin Cutler, Richard Deeley, Gregorio Gervasio, Atsuo Kawaguchi, Keiji Kojima, Woobin Lee, Takeshi Miyazaki, Yatin Mundkur, Vinay Naik, Kiyokazu Nishioka, Toru Nojiri, John O'Donnell, Sarang Padalkar
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Patent number: 7262755Abstract: A multi-tone display matrix display device including a matrix display panel having a matrix having plural X and Y direction signal lines lying at right angles to each other, intersecting points on the matrix being pixels of an image, an X direction driving section for sequentially scanning X direction signal lines to provide image signals, a Y direction driving section for driving the Y direction signal lines in synchronism with the scanning of the X direction signal lines to sequentially provide select signals to the Y direction signal lines, an A-D converter section for converting an analog signal into a digital signal, a voltage generating section for generating signals at plural voltage levels, and a selector section for selecting an output signal from the voltage generating section based on the output from A-D converter section and providing to output to the X direction driving section as an image signal.Type: GrantFiled: March 24, 2005Date of Patent: August 28, 2007Assignee: Hitachi, Ltd.Inventors: Hiroyuki Mano, Kiyokazu Nishioka, Toshio Futami, Kiyoshige Kinugawa
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Publication number: 20070182764Abstract: A multi-tone display matrix display device including a matrix display panel having a matrix having plural X and Y direction signal lines lying at right angles to each other, intersecting points on the matrix being pixels of an image, an X direction driving section for sequentially scanning X direction signal lines to provide image signals, a Y direction driving section for driving the Y direction signal lines in synchronism with the scanning of the X direction signal lines to sequentially provide select signals to the Y direction signal lines, an A-D converter section for converting an analog signal into a digital signal, a voltage generating section for generating signals at plural voltage levels, and a selector section for selecting an output signal from the voltage generating section based on the output from A-D converter section and providing to output to the X direction driving section as an image signal.Type: ApplicationFiled: April 5, 2007Publication date: August 9, 2007Inventors: Hiroyuki Mano, Kiyokazu Nishioka, Toshio Futami, Kiyoshige Kinugawa
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Publication number: 20070130401Abstract: An integrated multimedia system having a multimedia processor is disposed in an integrated circuit having a first host processor system coupled to the multimedia processor and a second local processor disposed within the multimedia processor for controlling the operation of the multimedia processor. A data transfer switch is coupled to the second processor for transferring data to various modules of the processor, at least one of which is a data cache. The data transfer switch transfers data in either direction between the cache and a module within the processor. A data streamer schedules simultaneous data transfers among the various-modules disposed within the multimedia processor in accordance with corresponding channel allocations. An interface unit is coupled to the data streamer and has a plurality of input/output (I/O) device driver units. A plurality of external I/O devices are coupled to the plurality of I/O device driver units via a multiplexer.Type: ApplicationFiled: October 30, 2006Publication date: June 7, 2007Inventors: David Baker, Christopher Basoglu, Benjamin Cutler, Richard Deeley, Gregorio Gervasio, Atsuo Kawaguchi, Keiji Kojima, Woobin Lee, Takeshi Miyazaki, Yatin Mundkur, Vinay Naik, Kiyokazu Nishioka, Kiyokazu Nishioka, Toru Nojiri, John O'Donnell, Sarang Padalkar
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Patent number: 7212181Abstract: This specification discloses a novel multi-tone display matrix display device.Type: GrantFiled: July 25, 2000Date of Patent: May 1, 2007Assignee: Hitachi, Ltd.Inventors: Hiroyuki Mano, Kiyokazu Nishioka, Toshio Futami, Kiyoshige Kinugawa
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Publication number: 20060053271Abstract: An object of the present invention is to provide a processor that can execute many computations with a small number of instruction codes. As far as multimedia processing is concerned, a plurality of computations of a same type are often executed concurrently and hence a plurality of computing units having a same function are used and mode information for controlling the plurality of units by an instruction unit for one computing unit is prepared in each instruction to execute a plurality of computations with a single instruction.Type: ApplicationFiled: September 1, 2005Publication date: March 9, 2006Inventors: Kiyokazu Nishioka, Kazuhiko Tanaka, Yoshifumi Fujikawa, Toru Nojiri, Keiji Kojima, Koichi Terada, Yoshiki Kurokawa, Koji Hosoki
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Patent number: 6965981Abstract: As far as multimedia processing is concerned, a plurality of computations of a same type are often executed concurrently and hence a plurality of computing units having a same function are used and mode information for controlling the plurality of units by an instruction unit for one computing unit is prepared in each instruction to execute a plurality of computations with a single instruction.Type: GrantFiled: January 24, 2002Date of Patent: November 15, 2005Assignee: Renesas Technology CorporationInventors: Kiyokazu Nishioka, Kazuhiko Tanaka, Yoshifumi Fujikawa, Toru Nojiri, Keiji Kojima, Koichi Terada, Yoshiki Kurokawa, Koji Hosoki
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Publication number: 20050200581Abstract: A multi-tone display matrix display device including a matrix display panel having a matrix having plural X and Y direction signal lines lying at right angles to each other, intersecting points on the matrix being pixels of an image, an X direction driving section for sequentially scanning X direction signal lines to provide image signals, a Y direction driving section for driving the Y direction signal lines in synchronism with the scanning of the X direction signal lines to sequentially provide select signals to the Y direction signal lines, an A-D converter section for converting an analog signal into a digital signal, a voltage generating section for generating signals at plural voltage levels, and a selector section for selecting an output signal from the voltage generating section based on the output from A-D converter section and providing to output to the X direction driving section as an image signal.Type: ApplicationFiled: March 24, 2005Publication date: September 15, 2005Inventors: Hiroyuki Mano, Kiyokazu Nishioka, Toshio Futami, Kiyoshige Kinugawa
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Publication number: 20040255058Abstract: An integrated multimedia system has a multimedia processor disposed in an integrated circuit. The system comprises a first host processor system which is coupled to the multimedia processor. A second local processor is disposed within the multimedia processor which controls the operation of the multimedia processor. A data transfer switch is disposed within the multimedia processor and coupled to the second processor which transfers data to various modules of the multimedia processor. A fixed function unit is disposed within the multimedia processor, coupled to the second processor and the data transfer switch and configured to perform three dimensional graphic operations.Type: ApplicationFiled: June 15, 2004Publication date: December 16, 2004Inventors: David Baker, Christopher Basoglu, Benjamin Cutler, Richard Deeley, Gregorio Gervasio, Atsuo Kawaguchi, Keiji Kojima, Woobin Lee, Takeshi Miyazaki, Yatin Mundkur, Vinay Naik, Kiyokazu Nishioka, Toru Nojiri, John O'Donnell, Sarang Padalkar
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Publication number: 20040221071Abstract: An integrated multimedia system has a multimedia processor disposed in an integrated circuit. The system comprises a first host processor system which is coupled to the multimedia processor. A second local processor is disposed within the multimedia processor which controls the operation of the multimedia processor. A data transfer switch is disposed within the multimedia processor and coupled to the second processor which transfers data to various modules of the multimedia processor. A fixed function unit is disposed within the multimedia processor, coupled to the second processor and the data transfer switch and configured to perform three dimensional graphic operations.Type: ApplicationFiled: February 5, 2001Publication date: November 4, 2004Inventors: David Baker, Christopher Basoglu, Benjamin Cutler, Richard Deeley, Gregorio Gervasio, Atsuo Kawaguchi, Keiji Kojima, Woobin Lee, Takeshi Miyazaki, Yatin Mundkur, Vinay Naik, Kiyokazu Nishioka, Toru Nojiri, John O'Donnell, Sarang Padalkar
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Publication number: 20040105500Abstract: In a system in which a CPU 2 and a motion compensation coprocessor 1 are interconnected via a bus 3, the motion compensation coprocessor 1 has computation descriptor registers 12 that are chainable on an individual process basis, and comprises means for reading reference data in accordance with the contents of the computation descriptor registers, means for outputting a computation result, a read/storage circuit 18 for storing reference data, a write/storage circuit 19 for storing a computation result, and a motion compensation computing unit 17.Type: ApplicationFiled: March 28, 2003Publication date: June 3, 2004Inventors: Koji Hosogi, Kiyokazu Nishioka, Yukio Fujii, Yoshifumi Fujikawa, Shigeki Higashijima
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Publication number: 20030222877Abstract: A processor has a data cache that is connected to a coprocessor via a bus, in which the coprocessor writes results of operations performed within the coprocessor in the data cache inside the processor. The data cache is equipped with a function to write data in a tag memory or a data memory according to a write request from the bus, and the coprocessor is equipped with an address generation device that is capable of designating an address of the data cache as a write address.Type: ApplicationFiled: May 16, 2003Publication date: December 4, 2003Applicant: HITACHI, LTD.Inventors: Kazuhiko Tanaka, Koji Hosogi, Sigeki Higashijima, Kiyokazu Nishioka
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Publication number: 20020099924Abstract: An object of the prevent invention is to provide a processor that can execute many computations with a small number of instruction codes.Type: ApplicationFiled: January 24, 2002Publication date: July 25, 2002Applicant: Hitachi, Ltd.Inventors: Kiyokazu Nishioka, Kazuhiko Tanaka, Yoshifumi Fujikawa, Toru Nojiri, Keiji Kojima, Koichi Terada, Yoshiki Kurokawa, Koji Hosoki
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Patent number: 6401190Abstract: An object of the prevent invention is to provide a processor that can execute many computations with a small number of instruction codes. As far as multimedia processing is concerned, a plurality of computations of a same type are often executed concurrently and hence a plurality of computing units having a same function are used and mode information for controlling the plurality of units by an instruction unit for one computing unit is prepared in each instruction to execute a plurality of computations with a single instruction.Type: GrantFiled: September 12, 1997Date of Patent: June 4, 2002Assignee: Hitachi, Ltd.Inventors: Kiyokazu Nishioka, Kazuhiko Tanaka, Yoshifumi Fujikawa, Toru Nojiri, Keiji Kojima, Koichi Terada, Yoshiki Kurokawa, Koji Hosoki
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Patent number: 6347344Abstract: An integrated multimedia system has a multimedia processor disposed in an integrated circuit. The system comprises a first host processor system which is coupled to the multimedia processor. A second local processor is disposed within the multimedia processor which controls the operation of the multimedia processor. A data transfer switch is disposed within the multimedia processor and coupled to the second processor which transfers data to various modules of the multimedia processor. A fixed function unit is disposed within the multimedia processor, coupled to the second processor and the data transfer switch and configured to perform three dimensional graphic operations. A data streamer is coupled to the data transfer switch, and configured to schedule simultaneous data transfers among a plurality of modules disposed within the multimedia processor in accordance with the corresponding channel allocations.Type: GrantFiled: October 14, 1998Date of Patent: February 12, 2002Assignees: Hitachi, Ltd., Equator Technologies, Inc.Inventors: David Baker, Christopher Basoglu, Benjamin Cutler, Richard Deeley, Gregorio Gervasio, Atsuo Kawaguchi, Keiji Kojima, Woobin Lee, Takeshi Miyazaki, Yatin Mundkur, Vinay Naik, Kiyokazu Nishioka, Toru Nojiri, John O'Donnell, Sarang Padalkar
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Patent number: 6191767Abstract: This specification discloses a novel multi-tone display matrix display device.Type: GrantFiled: June 6, 1995Date of Patent: February 20, 2001Assignee: Hitachi, Ltd.Inventors: Hiroyuki Mano, Kiyokazu Nishioka, Toshio Futami, Kiyoshige Kinugawa
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Patent number: 6191765Abstract: This specification discloses a novel multi-tone display matrix display device.Type: GrantFiled: November 10, 1998Date of Patent: February 20, 2001Assignee: Hitachi, Ltd.Inventors: Hiroyuki Mano, Kiyokazu Nishioka, Toshio Futami, Kiyoshige Kinugawa
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Patent number: 6041399Abstract: In the case of constituting a processing unit having the characteristic of a VLIW type processing unit and the characteristic of a pipeline type processing unit, since reference to the result of operations is made among a plurality of processing units executing in parallel the operations, transfer of the register file is frequently generated among the processing units, resulting in insufficient effect of the high speed operations. In view of solving this problem, the predicate registers are provided and moreover a means for broadcasting the update data of the predicate register to all processing units is also provided. Thereby, operations for obtaining branching condition and numerical value can be realized in different processing units and the number of steps of the processing program can be reduced.Type: GrantFiled: June 27, 1997Date of Patent: March 21, 2000Assignee: Hitachi, Ltd.Inventors: Koichi Terada, Keiji Kojima, Yoshifumi Fujikawa, Tohru Nojiri, Kiyokazu Nishioka
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Patent number: 5893143Abstract: Each processing unit 110a to 110d has an individual cache memory 100a to 100d. When the cache memories read an instruction from a main storage 5, an instruction field is distributed to the cache memories. Each cache memory is controlled by a common control circuit 20. A compiler operates to schedule the processes so as to focus the processes to be executed on a specific processing unit. According to the scheduled processes, the volumes of the cache memories 100a to 100d are specified according to each execution ratio of the corresponding processing units to the cache memories. In the foregoing arrangement, a processor provides the processing units controlled by a sole program counter and improves processing by improving the efficiency of the cache memory. Further, the processor improves the efficiency of the cache memory by deleting unnecessary codes.Type: GrantFiled: June 21, 1996Date of Patent: April 6, 1999Assignee: Hitachi, Ltd.Inventors: Kazuhiko Tanaka, Keiji Kojima, Kiyokazu Nishioka, Tohru Nojiri, Yoshifumi Fujikawa, Masao Ishiguro