Patents by Inventor Kiyomasa Kamei

Kiyomasa Kamei has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10136562
    Abstract: An underwater data center includes an electronic device; a housing member that houses the electronic device and that is configured to be disposed under water; and a heat exchanger that is provided at the housing member and that is configured to discharge, into the water, heat discharged from the electronic device, with a face of the heat exchanger that discharges the heat making contact with the water, an opening being formed in a bottom face of the housing member and placing an inside of the housing member in communication with the water.
    Type: Grant
    Filed: July 3, 2017
    Date of Patent: November 20, 2018
    Assignee: FUJITSU LIMITED
    Inventors: Naofumi Kosugi, Susumu Takahashi, Kiyomasa Kamei
  • Publication number: 20180054916
    Abstract: An underwater data center includes an electronic device; a housing member that houses the electronic device and that is configured to be disposed under water; and a heat exchanger that is provided at the housing member and that is configured to discharge, into the water, heat discharged from the electronic device, with a face of the heat exchanger that discharges the heat making contact with the water, an opening being formed in a bottom face of the housing member and placing an inside of the housing member in communication with the water.
    Type: Application
    Filed: July 3, 2017
    Publication date: February 22, 2018
    Applicant: FUJITSU LIMITED
    Inventors: NAOFUMI KOSUGI, Susumu TAKAHASHI, Kiyomasa Kamei
  • Patent number: 5498893
    Abstract: A semiconductor device includes a semiconductor layer which has a first surface, and a second surface which is comparatively lower than the first surface. The semiconductor device also has a first material layer formed over the second surface, which includes a first inorganic material which has a hardness exceeding that of the semiconductor layer. The semiconductor device also includes a second material layer which has a hardness less than that of the first material layer, and which is formed in a gap between a sidewall of the first material layer and a sidewall between the first and second surfaces. The first surface of the semiconductor layer is formed by lapping until the first surface of the semiconductor layer is impeded by the first material layer so that the first surface of the semiconductor layer is substantially flush with a top surface of the first material layer.
    Type: Grant
    Filed: June 7, 1995
    Date of Patent: March 12, 1996
    Assignee: Fujitsu Limited
    Inventors: Shouji Usui, Taketoshi Inagaki, Kiyomasa Kamei, Takeshi Matsutani, Kazunori Imaoka
  • Patent number: 5162254
    Abstract: A method for producing a semiconductor device on a semiconductor layer provided on an insulator layer comprises the steps of providing an opening on the semiconductor layer to expose a top surface of the insulator layer, depositing a first material layer that has a hardness exceeding the hardness of the semiconductor layer on the semiconductor layer including the exposed top surface, and patterning the first material layer such that a patterned region of the first inorganic material is left in the opening with a gap separating the patterned region from the side wall of the semiconductor layer.
    Type: Grant
    Filed: October 31, 1990
    Date of Patent: November 10, 1992
    Assignee: Fujitsu Limited
    Inventors: Shouji Usui, Taketoshi Inagaki, Kiyomasa Kamei, Takeshi Matsutani, Kazunori Imaoka