Patents by Inventor Kiyonori Kajiyana

Kiyonori Kajiyana has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 5804505
    Abstract: Disclosed herein is a method of producing a semiconductor device which includes the steps of forming a hole in an insulating film covering a semiconductor substrate, forming a titanium nitride layer on surfaces of the hole and the insulating film, depositing tungsten on the titanium nitride layer with filling the hole to thereby form a blanket tungsten layer, etching back the blanket tungsten layer by a plasma gas including fluorine until the titanium nitride layer is exposed to thereby form a tungsten plug filling the hole, cleaning the titanium nitride layer to remove fluorine adhering to and remaining on the titanium nitride layer, and forming an aluminum layer on the cleaned titanium layer and the tungsten plug.
    Type: Grant
    Filed: July 12, 1996
    Date of Patent: September 8, 1998
    Assignee: NEC Corporation
    Inventors: Yoshiaki Yamada, Kiyonori Kajiyana
  • Patent number: 5798544
    Abstract: Disclosed herein is a semiconductor memory device including a plurality of memory cells each includes an active region which is defined in a column direction by a pair of trench isolation regions formed in a semiconductor substrate and in a row direction by an isolation gate conductor lines formed on a first gate insulating film covering the substrate, a source and a drain region selectively formed in the active region to define a channel region of a cell transistor, a second gate insulating film formed on the channel region, a word line formed on the second gate insulating film, a first insulating film covering the active region and the word line, a bit line formed on the first insulating film to overlap with the isolation gate conductor, a bit line connection conductor formed in the first insulating film to connect the drain region to the bit line with being in contact with the sidewall surface of the bit line, a second insulating film covering the bit line and the first insulating film, and a storage capac
    Type: Grant
    Filed: May 13, 1994
    Date of Patent: August 25, 1998
    Assignee: NEC Corporation
    Inventors: Shuichi Ohya, Masato Sakao, Yoshihiro Takaishi, Kiyonori Kajiyana, Takeshi Akimoto, Shizuo Oguro, Seiichi Shishiguchi