Abstract: To provide a data fetch circuit, which reliably cuts off transmission of a high impedance state of a data strobe signal even if a manufacture condition or an operation condition is changed, and a control method thereof. The data fetch circuit includes an RL measuring part 10 measuring a latency measurement value RLB from an input of a read instruction signal RD to a valid edge of a data strobe signal DQS and an RL count comparing part 30 outputting a BL count start signal BST giving an instruction of a cancel of the cut-off of the data strobe signal DQS after standing by during the time based on the latency measurement value RLB in accordance with an input of a delay read instruction signal RDD.

Abstract: A semiconductor device that performs refresh tests of a plurality of individual memories built into the same chip and prevents excessive testing during the refresh test. When a first testing circuit enters a wait state, the first testing circuit issues a refresh command REF to a first memory circuit. Then, the first memory circuit refreshes the memory cells until a second testing circuit enters the wait state. That is, since the memory cells of the first memory circuit are refreshed until the writing to a second memory circuit ends, the refresh test time of the first and second memory circuits are the same.

Abstract: To provide a data fetch circuit, which reliably cuts off transmission of a high impedance state of a data strobe signal even if a manufacture condition or an operation condition is changed, and a control method thereof. The data fetch circuit includes an RL measuring part 10 measuring a latency measurement value RLB from an input of a read instruction signal RD to a valid edge of a data strobe signal DQS and an RL count comparing part 30 outputting a BL count start signal BST giving an instruction of a cancel of the cut-off of the data strobe signal DQS after standing by during the time based on the latency measurement value RLB in accordance with an input of a delay read instruction signal RDD.

Abstract: To provide a data fetch circuit, which reliably cuts off transmission of a high impedance state of a data strobe signal even if a manufacture condition or an operation condition is changed, and a control method thereof. The data fetch circuit includes an RL measuring part 10 for measuring a latency measurement value RLB from an input of a read instruction signal RD to a valid edge of a data strobe signal DQS and an RL count comparing part 30 for outputting a BL count start signal BST for giving an instruction of a cancel of the cut-off of the data strobe signal DQS after standing by during the time based on the latency measurement value RLB in accordance with an input of a delay read instruction signal RDD.

Abstract: A semiconductor device that performs refresh tests of a plurality of individual memories built into the same chip and prevents excessive testing during the refresh test. When a first testing circuit enters a wait state, the first testing circuit issues a refresh command REF to a first memory circuit. Then, the first memory circuit refreshes the memory cells until a second testing circuit enters the wait state. That is, since the memory cells of the first memory circuit are refreshed until the writing to a second memory circuit ends, the refresh test time of the first and second memory circuits are the same.

Abstract: A semiconductor device having multiple memory circuits and one or more logic sections includes a single test circuit for testing all of the memory circuits. The test circuit includes a test section that controls the memory circuits, for example, by initiating a read operation, with a control signal. Comparison/determination circuits, which correspond to the memory circuits, compare the data read from the memory circuits with expected value data, and generate determination signals. Since the various memory circuits are different distances (wire lengths) from the test section, a control section is provided which adds a delay to the control signal provided to the various memory circuits so that the memory circuits all receive the control signal at about the same time and perform their respective read operations at the same time.

Abstract: A semiconductor memory device, such as a DRAM, includes a memory cell array and pairs of bit lines connected to the memory cells in the array. A precharge circuit is connected the bit line pairs and selectively provides the bit line pairs with a reference power supply voltage when the memory cells are being accessed and a precharge voltage when the memory cells are not being accessed. A correction circuit adjusts the precharge voltage in accordance with a difference between the precharge voltage and the reference power supply voltage so that the precharge voltage becomes substantially equal to the reference power supply voltage. A retention mode determination circuit detects when the memory device is in a retention mode (powered down state) and prevents access to the memory cells at this time.

Abstract: The semiconductor device according to the present invention includes a semiconductor substrate of a first conductive type. A well area of the first conductive type is formed in the substrate. The well area has higher concentration of impurity than that of the substrate. The well area includes a first element. The first element is of a second conductive type different from the first conductive type. A second element of the second conductive type formed in the substrate. The first element is isolated from the second element by a field oxide.

Abstract: An electrically programmable and electrically erasable non-volatile semiconductor memory device having an array of single transistor cells is provided. The disclosed device protects against reading faults even in the event that adjacent transistors may be over erased. Each of the cell transistor rows has an associated word line and an associated select element. The select elements are connected to the sources of their associated cell transistors and are arranged to activate those cell transistors only when their associated word line is selected. Cell transistors in unselected rows are not activated and thus do not interfere with reading even if they are in an over erased condition.

Abstract: A semiconductor memory device has a first control signal is externally input to an input buffer circuit. A second control signal output from the input buffer circuit is input to an internal circuit. The internal circuit comprises a memory cell array having a number of memory cells and peripheral circuits for writing and reading cell information in and from the memory cells, and the writing and reading operations are executed based on the second control signal. Read data output from the internal circuit is input to an output buffer, which outputs the read data as output data. Power from a common power supply is supplied to the input buffer circuit and the output buffer. A noise-remove signal generator, which is connected to the input buffer circuit, functions based on either one of the first control signal and the second control signal to generate a noise remove signal in synchronism with an output timing of the output data.

Abstract: A programmable logic device includes: a programmable AND array; an OR array operatively connected to the AND array; a plurality of external terminals; and a plurality of cell blocks operatively connected to the AND array and OR array and provided for each of the plurality of external terminals, each receiving two output signals from the OR array and outputting a signal to a corresponding external terminal based on the two output signals. By controlling an input/output of an input signal and an internally produced signal and a feedback thereof to the AND array, it is possible to realize various logic constitutions and develop a degree of freedom of the logic design in the entire device.