Abstract: In a semiconductor device of a polysilicon gate electrode structure having three or more different Fermi levels, a P type polysilicon having a lowest Fermi level is disposed on a first N type surface channel MOS transistor. A first N type polysilicon having a highest Fermi level is disposed on a second N type surface channel MOS transistor. A second N type polysilicon having an intermediate Fermi level between the highest and the lowest Fermi levels and doped with both an N type impurity and a P type impurity is disposed on a P channel MOS transistor.

Abstract: The present invention provides a resin bond grindstone and method of manufacturing a semiconductor chip using the grindstone that provide a semiconductor device with high reliability even when a thickness of the semiconductor chip is thinned, and specifically provides followings: [1] A resin bond grindstone which comprises grains coated with at least one magnetic metal selected from a group consisting of cobalt, iron, manganese, chromium, vanadium and alloys thereof, and a resin, where the grains coated with the magnetic metal are dispersed in the resin; and [2] A method of manufacturing a semiconductor chip including a step of grinding a semiconductor wafer using the resin bond grindstone as described in above item [1] and a step of dicing the ground semiconductor wafer.

Abstract: After a gate electrode made of a material containing a refractory metal is formed, the gate electrode is oxidized to form an oxide film for covering an exposed side surface of the gate electrode, at a predetermined temperature in an initial oxidization phase, and thereafter, the gate electrode is oxidized at a temperature higher than the predetermined temperature in an additional oxidization phase. Since the side surface of the gate electrode is covered with the oxide film in the initial oxidization phase, the refractory metal is prevented from being scattered from the side surface of the gate electrode in the additional oxidization phase. The layer resistance of the film containing the refractory metal is reduced because the additional oxidization phase is performed at the higher temperature.

Abstract: A gate dielectric film, a poly-silicon film, a film of a refractory metal such as tungsten, and a gate cap dielectric film are sequentially laminated on a semiconductor substrate. The gate cap dielectric film and the refractory metal film are selectively removed by etching. Thereafter, a double protection film including a silicon nitride film and a silicon oxide film is formed on side surfaces of the gate cap dielectric film, the refractory metal film, and the poly-silicon film. The poly-silicon film is etched using the double protection film as a mask. Thereafter, the semiconductor substrate is light oxidized to form a silicon oxide film on side surfaces of the poly-silicon film. Accordingly, a junction leakage of a MOSFET having a gate electrode of a poly-metal structure, particularly, a memory cell transistor of a DRAM, can be further reduced.

Abstract: The electron beam is irradiated several times at predetermined intervals to the wafer surface on which the plugs are exposed in the course of the manufacturing process so that the pn junction is in the reverse bias state. Then, the irradiation conditions of the electron beam are changed while monitoring the charging voltage on the plug surface, and the secondary electron signals of the circuit pattern are obtained under the irradiation conditions that the charging is within a desired range, thereby evaluating the leakage property. Since the charging voltage of the pn junction is relaxed depending on the magnitude of the leakage current during the interval, the leakage property is evaluated based on the luminance signals of the voltage contrast image. By measuring the charging voltage and setting it within a desired range, the evaluation result reflects the state in the actual operation. Therefore, the accuracy is enhanced.

Abstract: A semiconductor chip having a thickness of 130 micrometers or less includes a mechanically ground bottom surface corresponding to a central circuit area, and a polished bottom surface corresponding to a peripheral scribe area.

Abstract: In manufacturing a semiconductor device, the first gettering layer is formed on the backside of a wafer, and the second gettering layers are then formed on the backside and side surfaces of a chip, allowing these gettering layers to serve as trapping sites against metallic contamination that generated after backside grinding in assembly processes.

Abstract: A method for forming a semiconductor memory device includes the steps of: implanting a dopant in a semiconductor substrate; heat treating the semiconductor substrate in an oxidizing ambient to diffuse the dopant for forming diffused regions in the semiconductor substrate; and forming memory cells each including a MOS transistor having the diffused regions as source/drain regions.

Abstract: A method for manufacturing a MOS transistors in a semiconductor device includes the step of implanting a dopant in a channel layer or source/drain regions by using a multi-step implantation and an associated multi-step heat treatment, wherein the multi-step implantation includes a number of steps of implantation each for implanting the dopant at a dosage lower than 1×1013/cm2. The total dosage of the multi-step implantation ranges between 1×1013/cm2 and 3×1013/cm2.

Abstract: A method for manufacturing a DRAM device includes a hydrogenating step conducted to source/drain diffused regions in a hydrogen ambient at a substrate temperature not lower than 350 degrees C., and a dehydrogenating step in an inactive gas ambient at a substrate temperature of lower than 350 degrees C., before a packaging step. If a defective cell having a lower refreshing time is found in the test before the packaging step, the defective cell is replaced by a redundant cell. The resultant DRAM has a lower degradation in the refreshing characteristic after the packaging step.

Abstract: A method for manufacturing a DRAM device includes the step of implanting phosphor at a specified dosage and heat treating the implanted phosphor for diffusion thereof to form source/drain regions, and implanting fluorine into the source/drain regions and heat treating the implanted fluorine for diffusion thereof. The resultant DRAM memory cell has a larger data storage capability due to lower junction leakage current caused by vacancy type defects formed in the metallurgical junction between the source/drain regions and the channel region.

Abstract: Disclosed is a technique for reducing the leak current by reducing contamination of metal composing a polymetal gate of a MISFET: Of a polycrystalline silicon film, a WN film, a W film, and a cap insulating film formed on a gate insulating film on a p-type well (semiconductor substrate), the cap insulating film, the W film, and the WN film are etched and the over-etching of the polycrystalline silicon film below them is performed. Then, a sidewall film is formed on sidewalls of these films. Thereafter, after etching the polycrystalline silicon film with using the sidewall film as a mask, a thermal treatment is performed in an oxidation atmosphere, by which a light oxide film is formed on the sidewall of the polycrystalline silicon film. As a result, the contamination on the gate insulating film due to the W and the W oxide can be reduced, and also, the diffusion of these materials into the semiconductor substrate (p-type well) and the resultant increase of the leak current can be prevented.

Abstract: A semiconductor memory device includes a semiconductor substrate, and gate electrodes formed for a transistor on the semiconductor substrate through a gate insulating film. A gate length of the gate electrode is longer than a minimum processing dimension. The semiconductor memory device may further include a first diffusion layer formed in a surface of the semiconductor substrate to function as one of a source and a drain, and a second diffusion layer formed in the surface of the semiconductor substrate to function as the other of the source and the drain. The shortest distance between the first diffusion layer and the second diffusion layer is proportional to the gate length. In this case, the semiconductor memory device may further include a gate insulating film formed on the semiconductor substrate and extending over the first diffusion layer and the second diffusion layer. The gate electrode is formed on the gate insulating film.

Abstract: Disclosed is a technique for reducing the leak current by reducing contamination of metal composing a polymetal gate of a MISFET. Of a polycrystalline silicon film, a WN film, a W film, and a cap insulating film formed on a gate insulating film on a p-type well (semiconductor substrate), the cap insulating film, the W film, and the WN film are etched and the over-etching of the polycrystalline silicon film below them is performed. Then, a sidewall film is formed on sidewalls of these films. Thereafter, after etching the polycrystalline silicon film with using the sidewall film as a mask, a thermal treatment is performed in an oxidation atmosphere, by which a light oxide film is formed on the sidewall of the polycrystalline silicon film. As a result, the contamination on the gate insulating film due to the W and the W oxide can be reduced, and also, the diffusion of these materials into the semiconductor substrate (p-type well) and the resultant increase of the leak current can be prevented.

Abstract: A reduction of the junction electric field intensity is accomplished in the semiconductor regions for the sources and drains of field effects transistors. For this purpose, a structure is provided where the gate electrodes 9 of the MIS·FETQs for memory cell selection of a DRAM are buried within the trenches 7a and 7b created in the semiconductor substrate 1. The bottom corners within the trench 7b are rounded so as to have a radius of curvature in accordance with the sub-threshold coefficient of the MIS·FETQs for memory cell selection. In addition, the gate insulating film 8 within the trench 7b is made to have a laminated structure of a thermal oxide film and a CVD film.

Abstract: An active region 1 has diffusion layers 6a to 8a sandwiched by plural word-lines. The diffusion layer 6a sandwiched by word-lines 2 and 3 locates at a center of the active region 1 and connects to a bit-line through a contact. The diffusion layers 7a and 8a sandwiched by word-lines 2 and 3 and both sides of the active region 1 respectively are connected to capacitor portions. A cell structure is formed of two cell transistors. One cell transistor has the word-line 2 as a gate and the diffusion layers 6a and 7a as source and drain, respectively. The other cell transistor has the word-line 3 as a gate and the diffusion layers 6a and 8a as a source and a drain, respectively. The diffusion layers 7a and 8a placed outside of the active region 1 are n-type and have high carrier concentration of n-type at the region separated from word-lines than to the region close to the word-lines 2 and 3. A p-type substrate exhibits low concentration at the region outside the word-lines.

Abstract: In semiconductor integrated circuit devices having fine memory cells and a reduced bit line capacity, a side wall insulating film of gate electrodes (word line) is made of silicon nitride and a side wall insulating film of silicon oxide having a dielectric constant smaller than that of the side wall insulating film made of silicon nitride, thereby reducing the capacity for a word line formed over the gate electrode (word line). By setting the level of the upper end of the side wall insulating film made of silicon oxide to be lower than that of the top face of a cap insulating film, the diameter in the upper part of a plug buried in each space (contact holes) between the gate electrodes is set larger than the diameter in the bottom part to assure a contact area between the contact hole and a through hole formed on the contact hole.

Abstract: A semiconductor device has a reduced contact resistance between a tungsten film and a polysilicon layer and has a gate electrode prevented from being depleted for a reduced gate resistance. According to a method of fabricating such a semiconductor device, a semiconductor device having a gate electrode of a polymetal gate structure which comprises a three-layer structure having a tungsten (W) film, a tungsten nitride (WN) film, and a polysilicon (PolySi) layer, is manufactured by nitriding the sides of the gate electrode at a nitriding temperature ranging from 700° C. to 950° C. in an ammonia atmosphere after the gate electrode is formed and before side selective oxidization is performed on the gate electrode.

Abstract: In a semiconductor device of a polysilicon gate electrode structure having three or more different Fermi levels, a P type polysilicon having a lowest Fermi level is disposed on a first N type surface channel MOS transistor. A first N type polysilicon having a highest Fermi level is disposed on a second N type surface channel MOS transistor. A second N type polysilicon having an intermediate Fermi level between the highest and the lowest Fermi levels and doped with both an N type impurity and a P type impurity is disposed on a P channel MOS transistor.

Abstract: A reduction of the junction electric field intensity is accomplished in the semiconductor regions for the sources and drains of field effects transistors. For this purpose, a structure is provided where the gate electrodes 9 of the MIS.FETQs for memory cell selection of a DRAM are buried within the trenches 7a and 7b created in the semiconductor substrate 1. The bottom corners within the trench 7b are rounded so as to have a radius of curvature in accordance with the sub-threshold coefficient of the MIS.FETQs for memory cell selection. In addition, the gate insulating film 8 within the trench 7b is made to have a laminated structure of a thermal oxide film and a CVD film.