Patents by Inventor Kiyonori Yoshitomi

Kiyonori Yoshitomi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20150235926
    Abstract: A semiconductor device permitting the reduction of cost is disclosed. In a semiconductor package wherein electrode pads of a semiconductor chip and corresponding inner leads are electrically coupled with each other through a plurality of bonding wires, sensing wires (second and fourth bonding wires) are made thinner than other bonding wires (first and third bonding wires) coupled to inner leads same as those with the sensing wires coupled thereto, thereby reducing the cost of gold wires to attain the reduction in cost of the semiconductor package.
    Type: Application
    Filed: May 4, 2015
    Publication date: August 20, 2015
    Inventors: Kazuya FUKUHARA, Kiyonori Yoshitomi, Takehiko Ikegami, Yujiro Kawasoe
  • Patent number: 9040358
    Abstract: A semiconductor device permitting the reduction of cost is disclosed. In a semiconductor package wherein electrode pads of a semiconductor chip and corresponding inner leads are electrically coupled with each other through a plurality of bonding wires, sensing wires (second and fourth bonding wires) are made thinner than other bonding wires (first and third bonding wires) coupled to inner leads same as those with the sensing wires coupled thereto, thereby reducing the cost of gold wires to attain the reduction in cost of the semiconductor package.
    Type: Grant
    Filed: August 25, 2014
    Date of Patent: May 26, 2015
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Kazuya Fukuhara, Kiyonori Yoshitomi, Takehiko Ikegami, Yujiro Kawasoe
  • Publication number: 20140363926
    Abstract: A semiconductor device permitting the reduction of cost is disclosed. In a semiconductor package wherein electrode pads of a semiconductor chip and corresponding inner leads are electrically coupled with each other through a plurality of bonding wires, sensing wires (second and fourth bonding wires) are made thinner than other bonding wires (first and third bonding wires) coupled to inner leads same as those with the sensing wires coupled thereto, thereby reducing the cost of gold wires to attain the reduction in cost of the semiconductor package.
    Type: Application
    Filed: August 25, 2014
    Publication date: December 11, 2014
    Inventors: Kazuya FUKUHARA, Kiyonori YOSHITOMI, Takehiko IKEGAMI, Yujiro KAWASOE
  • Patent number: 8846455
    Abstract: A semiconductor device permitting the reduction of cost is disclosed. In a semiconductor package wherein electrode pads of a semiconductor chip and corresponding inner leads are electrically coupled with each other through a plurality of bonding wires, sensing wires (second and fourth bonding wires) are made thinner than other bonding wires (first and third bonding wires) coupled to inner leads same as those with the sensing wires coupled thereto, thereby reducing the cost of gold wires to attain the reduction in cost of the semiconductor package.
    Type: Grant
    Filed: February 25, 2013
    Date of Patent: September 30, 2014
    Assignee: Renesas Electronics Corporation
    Inventors: Kazuya Fukuhara, Kiyonori Yoshitomi, Takehiko Ikegami, Yujiro Kawasoe
  • Patent number: 8384229
    Abstract: A semiconductor device permitting the reduction of cost is disclosed. In a semiconductor package wherein electrode pads of a semiconductor chip and corresponding inner leads are electrically coupled with each other through a plurality of bonding wires, sensing wires (second and fourth bonding wires) are made thinner than other bonding wires (first and third bonding wires) coupled to inner leads same as those with the sensing wires coupled thereto, thereby reducing the cost of gold wires to attain the reduction in cost of the semiconductor package.
    Type: Grant
    Filed: October 27, 2010
    Date of Patent: February 26, 2013
    Assignee: Renesas Electronics Corporation
    Inventors: Kazuya Fukuhara, Kiyonori Yoshitomi, Takehiko Ikegami, Yujiro Kawasoe
  • Publication number: 20110101544
    Abstract: A semiconductor device permitting the reduction of cost is disclosed. In a semiconductor package wherein electrode pads of a semiconductor chip and corresponding inner leads are electrically coupled with each other through a plurality of bonding wires, sensing wires (second and fourth bonding wires) are made thinner than other bonding wires (first and third bonding wires) coupled to inner leads same as those with the sensing wires coupled thereto, thereby reducing the cost of gold wires to attain the reduction in cost of the semiconductor package.
    Type: Application
    Filed: October 27, 2010
    Publication date: May 5, 2011
    Inventors: Kazuya FUKUHARA, Kiyonori Yoshitomi, Takehiko Ikegami, Yujiro Kawasoe